Jobs in Tel Aviv-Yafo

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters. As a DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools—you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity. Key Responsibilities • DFT Architecture & Strategy • Be part of the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support • Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards • Design and implement DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG for high-end devices • Test Pattern Development & Optimization • Generate and optimize high-quality test and debug patterns for production • Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance • Drive test coverage and quality metrics to meet stringent manufacturing requirements • Cross-Functional Collaboration & Methodology Innovation • Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR • Participate in developing and maintaining cutting-edge DFT implementation flows • Automate and improve methodologies using advanced scripting and tools Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 4+ years of hands-on experience in DFT roles at semiconductor companies • Experience in DFT flows and architectures including JTAG/iJTAG, MBIST, Scan, and ATPG • Good understanding of logic design, verification, debug, and Static Timing Analysis (STA) • Scripting proficiency in Tcl, Perl, Python, or Shell for automation and innovation Preferred Qualifications • Master's degree in Electrical Engineering or related field • Experience with industry-standard EDA tools from Synopsys (TestMAX) or Siemens (Tessent) • Experience in chip bring-up and mass production activities • Background in advanced process technologies (7nm and below) • Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) and their specific test requirements • Excellent communication skills with ability to work effectively in global team environments We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. The Role and Its Impact Our firmware team develops the embedded firmware that brings Astera Labs' compute connectivity silicon to life, from boot and initialization through link management, telemetry, error handling, and diagnostics. This firmware runs on the embedded processors inside our chips and ships in data centers powering AI infrastructure around the world. Beyond the firmware, the team also develops the COSMOS SDK, the software layer customers and internal teams use to configure, monitor, update, and debug our devices in their systems. We are looking for an experienced firmware engineer and PCIe expert who enjoys working close to the hardware, owns features end to end, and has a proven track record of developing and debugging firmware both pre-silicon and post-silicon. You know PCIe in depth, from link training and enumeration to error handling and recovery, and you're the person others turn to when a PCIe link or device misbehaves. You understand the whole system, not just the chip: how our devices behave inside customer platforms, and how a customer requirement turns into firmware and SDK. You'll work alongside architects, design and verification engineers, validation teams, and our global firmware teams to take new products from early pre-silicon development through bring-up and into customer deployment. What You'll Be Doing • Having fun! by being part of a very strong and cohesive group. • Design and develop real-time embedded firmware in C, including low-level drivers and control logic for complex hardware blocks • Own PCIe firmware features end to end: link training, enumeration, error handling, and recovery • Develop and debug firmware pre-silicon (emulation) and lead post-silicon bring-up and debug in the lab • Debug complex PCIe and system-level issues with architecture, design, validation, and customer teams • Develop and extend the company SDK in step with firmware features • Support customer requests and adjust firmware and SDK development to meet their needs What We're Looking For Required: • BSc/MSc in Computer Science, Electrical Engineering, Computer Engineering, or a related field • 10+ years of hands-on experience as a firmware engineer • Proven experience in embedded and real-time firmware development • Strong programming skills in C on resource-constrained, bare-metal, or RTOS-based systems • Solid understanding of processor architecture, memory-mapped registers, interrupts, and HW/SW interaction • Expert-level knowledge of PCIe: LTSSM and link training, enumeration, configuration space, error handling (AER), and reset and recovery flows • Experience with PCIe protocol analyzers and exercisers (e.g., Teledyne LeCroy, Keysight) • Proven hands-on experience in both pre-silicon and post-silicon firmware development and debugging, including silicon bring-up of new SoCs • Strong debugging skills on real hardware using JTAG debuggers, logs, and register-level analysis • Broad system-level understanding of how silicon, firmware, SDK, host software, and platform interact, with the ability to turn customer requirements into technical solutions • A team player with excellent communication skills who works well in a collaborative, cross-site environment • Comfort with ambiguity and ownership in a fast-moving, high-growth company Location This position is based in our Tel Aviv, Israel office. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Principal Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters. As an Principal Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity. Key Responsibilities • Emulation Flow Execution & Implementation • Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging • Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies • Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market • System-Level Debug & Validation • Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs • Ensure rapid cycles from RTL to functional stability through systematic debug approaches • Own technical blocks and drive them to completion independently • Cross-Functional Collaboration • Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios • Ensure seamless hardware-software integration for AI infrastructure connectivity • Collaborate with Design and Verification teams to optimize emulation strategies Basic Qualifications • Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field • 10+ years of hands-on experience in Emulation at semiconductor companies • Deep expertise in emulation flows for large-scale chips using industry-standard emulators (Zebu, Palladium, or Veloce) • Strong background in SystemVerilog for developing, testing, and debugging complex SoC designs • Experience developing and maintaining execution flows for building, running, and debugging emulation models • "Can-do" approach with ability to own technical blocks and drive them to completion independently Preferred Qualifications • Master's degree in Electrical Engineering, Computer Engineering, or related field • Familiarity with EDA tools for Lint, Clock Domain Crossing (CDC), simulation, and synthesis • Proficiency in scripting languages such as Python or TCL for automation and flow enhancement • Experience with standard debug environments (e.g., Verdi) • Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) • Background in hardware-software co-verification methodologies We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up. If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us. As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the world’s largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale. Key Responsibilities • Execute SoC Top-level physical design and actively drive full-chip convergence • Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff • Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR) • Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon • Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration Basic Qualifications • B.Sc. or M.Sc. in Electrical Engineering • 5+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below) • Proven experience executing complex block or chip-level projects with a proactive, "can-do" approach and excellent communication skills • Deep hands-on expertise in RTL2GDS flows, including P&R, STA, Physical Verification (DRC/LVS), Formal Verification, low-power implementation (UPF/CPF), and EMIR • Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2 or Cadence Innovus) • Practical experience handling both complex macro/subsystem-level designs and Full-Chip integration Preferred Qualifications • Deep understanding of Power & Noise analysis (EM/IR) • Experience with DFT (Design for Test) integration into the physical design flow • Background in high-speed interfaces or data center protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects. As a Senior ASIC Design Engineer, you won't just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity. Key Responsibilities • Design Ownership & Implementation • Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support • Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions • Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams • Quality Assurance & Design Optimization • Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient • Apply design techniques to meet PPA (Power, Performance, Area) targets • Contribute to design quality through verification and validation activities • Methodology Innovation & Collaboration • Participate in design methodology improvements and tool automation initiatives • Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter • Collaborate effectively across teams to ensure seamless integration Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 3+ years of experience in logic design at semiconductor companies • Knowledge and experience in Verilog and/or SystemVerilog • Excellent communication skills with ability to work effectively across teams • Understanding of digital design principles and RTL coding best practices Preferred Qualifications • Master's degree in Electrical Engineering or related field • Knowledge of DDR and PCIe protocols and implementation • Understanding of power management techniques for low-power design • Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis • Proficiency in scripting languages such as Python or Perl • Experience with high-speed serial interface designs or connectivity protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the world’s most demanding AI and cloud environments. Key Responsibilities • Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip • Collaborate closely with Physical Design team to insure a full power integrity • Partner with Package Design engineers to perform Chip-Package co-analysis (CPM) • Understand root-cause analysis for voltage drop violations and EM risks Basic Qualifications • Bachelor's or Master's degree in Electrical Engineering or a related technical field • 7+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products • Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, or Cadence Voltus) • Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm) • Deep understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture • Deep understanding of EM and trade-offs between signal EM and power grid (PG) EM Preferred Experience • Familiarity with thermal analysis tools and their interaction with electrical performance • Experience working with sign-off criteria and margins for high-volume production chips • Good understanding of timing and P&R • Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution • Ability to write TCL scripts for STA and Fusion Compiler (FC) We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters. As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You won’t just execute tasks; you will define the Formal verification strategy for chips that drive the world’s largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications. Key Responsibilities • Own and develop formal verification environments from scratch through to sign-off • Apply formal verification methodologies and strategies to prove the correctness of intricate designs • Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements • Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs • Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently • Architect and develop generic, common formal functions and properties to be reused across multiple projects Basic Qualifications • Bachelor's degree in Electrical Engineering or a related technical field • 4+ years of hands-on experience in Formal Verification within semiconductor companies • Deep expertise in formal verification methodologies, tools, and flows • Strong understanding of RTL design and verification principles • Experience with industry-standard formal verification tools (Jasper, VC Formal, or similar) • Excellent communication skills, strong analytical thinking, and a proactive, "can-do" approach to problem-solving Preferred Qualifications • Track record of successfully taking complex blocks or subsystems through the entire formal verification lifecycle • Experience with SystemVerilog UVM-based design verification • Knowledge of networking standards (Ethernet, NVLink, UALink, PCIe) • Background in high-speed serial interface verification We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. The Role and Its Impact Our firmware team develops the embedded firmware that brings Astera Labs' compute connectivity silicon to life, from boot and initialization through link management, telemetry, error handling, and diagnostics. This firmware runs on the embedded processors inside our chips and ships in data centers powering AI infrastructure around the world. Beyond the firmware, the team also develops the COSMOS SDK, the software layer customers and internal teams use to configure, monitor, update, and debug our devices in their systems. We are looking for an experienced firmware engineer who enjoys working close to the hardware, owns features end to end, and is equally comfortable in a pre-silicon emulation environment and in the lab with real silicon. You understand the whole system, not just the chip: how our devices behave inside customer platforms, and how a customer requirement turns into firmware and SDK. You'll work alongside architects, design and verification engineers, validation teams, and our global firmware teams to take new products from early pre-silicon development through bring-up and into customer deployment. What You'll Be Doing • Having fun! by being part of a very strong and cohesive group. • Design, implement, and maintain real-time embedded firmware in C for high-performance connectivity • Develop low-level drivers, initialization flows, interrupt handling, and control logic for complex hardware blocks • Bring up and debug firmware in pre-silicon environments (emulation) ahead of tape-out, and on silicon after it arrives • Work closely with architecture, design, and verification teams to define HW/FW interfaces and to resolve issues across the hardware/software boundary • Triage and resolve firmware issues reported by validation, product applications, and customers • Take part in design reviews and code reviews, and help improve our firmware quality, tooling, and development practices • Develop and extend the company SDK, including APIs, device management, firmware update, telemetry, and diagnostics capabilities, and keep it aligned with firmware features • Support customer requests and engagements together with product applications and field teams, analyze system-level use cases, and adjust firmware and SDK development to meet customer needs • Collaborate with firmware teams across sites to deliver features on schedule What We're Looking For Required: • BSc/MSc in Computer Science, Electrical Engineering, Computer Engineering, or a related field • 10+ years of hands-on experience as a firmware engineer • Proven experience in embedded and real-time firmware development • Strong programming skills in C on resource-constrained, bare-metal, or RTOS-based systems • Solid understanding of processor architecture, memory-mapped registers, interrupts, and HW/SW interaction • Strong debugging skills on real hardware using JTAG debuggers, logs, and register-level analysis • Broad system-level understanding of how silicon, firmware, SDK, host software, and platform interact, with the ability to turn customer requirements into technical solutions • A team player with excellent communication skills who works well in a collaborative, cross-site environment • Comfort with ambiguity and ownership in a fast-moving, high-growth company Advantage: • Experience with pre-silicon emulation platforms such as Cadence Palladium or Synopsys ZeBu • Knowledge of PCIe (link training, enumeration, configuration space, error handling) • Experience developing SDKs, host-side libraries, or APIs (C/C++ or Python) that interface with embedded firmware • Experience working directly with customers or supporting customer integration and field issues • Experience with silicon bring-up of new SoCs • Python scripting for test automation, debug, or data analysis We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Senior System Validation Engineer Astera Labs is seeking a motivated Senior System Validation Engineer to join our growing post-silicon validation team in Israel and support next-generation connectivity products for AI and data-center applications. In this role, you will perform system-level post-silicon validation, characterization, and debug across silicon, hardware, firmware, and software. You will support silicon bring-up and PVT/corner testing, develop and execute functional and system validation tests, analyze results, and work with cross-functional teams to identify and resolve complex system issues. This is a highly hands-on lab position. The primary location is Haifa, with temporary support at the Ramat Gan lab as needed. Key Responsibilities: • Develop and execute post-silicon functional and system validation from silicon bring-up through production readiness. • Run PVT, silicon corner, stress, characterization, and qualification testing across a wide range of operating conditions. • Develop validation tests to verify functionality, performance, stability, power, and operating margins. • Debug issues across silicon, hardware, firmware, drivers, and system software. • Validate high-speed interfaces such as PCIe, CXL, Ethernet/SerDes, and DDR, as well as common system interfaces. • Develop Python scripts and automation to improve validation coverage, regression, and test efficiency. • Analyze validation data, identify issues and trends, and drive problems to root cause and closure. • Work closely with hardware, architecture, firmware, software, design, and DV teams to investigate and resolve issues. • Support the transition of new silicon from initial bring-up to a qualified, production-ready product. • Operate system platforms and laboratory equipment to support validation and debug. • Document test results, issues, root cause, and recommendations and communicate findings clearly. Basic Qualifications: • B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, Computer Science, or a related field. • 6+ years of experience in post-silicon, system, hardware, or product validation. • Hands-on experience with SoC/silicon bring-up, functional validation, and system-level debug. • Experience developing and executing validation plans, test cases, and characterization experiments. • Strong Python scripting and test automation skills. • Strong hardware debugging, analytical, and problem-solving skills with the ability to work independently. • Experience debugging issues across hardware, firmware, and software. • Experience validating high-speed interfaces such as PCIe, Ethernet, SerDes, CXL, or DDR. • Hands-on experience working in a hardware or system validation laboratory. • Strong communication and cross-functional collaboration skills. Preferred Qualifications: • Experience with PVT validation, silicon corner testing, characterization, qualification, and margin analysis. • Experience with server, storage, networking, or AI infrastructure products. • Familiarity with PCIe/CXL architecture and high-speed SerDes technologies. • Experience with oscilloscopes, BERTs, protocol analyzers, traffic generators, or similar lab equipment. • Working knowledge of Python, firmware, Linux, and system-level software debugging. • Experience developing automated validation and regression environments. • Familiarity with Git and software development practices. • Experience with pre-silicon validation, emulation, or hardware prototyping. • Experience with system performance, throughput, latency, power, and stability testing. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly. As a Senior Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity. Key Responsibilities • Verification Environment Development • Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks • Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing • Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified • Coverage & Quality Assurance • Implement functional coverage models and analyze results to identify gaps in the verification process • Drive designs toward 100% verification closure through comprehensive test development • Contribute to verification methodology improvements and best practices • Debug & Cross-Functional Collaboration • Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle • Apply analytical skills and debugging techniques to solve intricate verification challenges • Collaborate effectively in a fast-paced, team-oriented R&D environment Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 3+ years of proven experience in ASIC verification within the semiconductor industry • Hands-on experience developing components within complex verification environments using SystemVerilog • Strong working knowledge of standard verification methodologies, specifically UVM • Sharp analytical mind with passion for debugging and technical problem-solving • Excellent communication skills with ability to thrive in collaborative R&D environments Preferred Qualifications • Master's degree in Electrical Engineering or related field • Familiarity with Formal Verification or Emulation flows • Basic proficiency in scripting languages such as Python or Tcl to automate verification tasks • Exposure to industry-standard protocols such as AMBA, PCIe, Ethernet, or CXL • Experience with assertion-based verification and constrained-random testing • Background in connectivity or networking silicon verification We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity. Key Responsibilities • Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments • Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence • Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments • Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners • Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient Basic Qualifications • B.Sc. in Electrical Engineering or Computer Engineering • 6+ years of hands-on experience in Static Timing Analysis (STA) at semiconductor companies, specifically working on advanced process technologies. (Note: Adjust years of experience based on the exact level you are targeting) • Deep expertise in multi-scenario STA, as well as timing and SDC constraint development and verification at the block and subsystem levels • Solid understanding of advanced margining methodologies, including OCV, AOCV, and POCV, from synthesis through to final sign-off • Solid knowledge of physical design flows (Synthesis, P&R, Physical Verification) and how they intersect with timing closure Preferred Experience • Experience developing and validating constraints using industry-standard tools like Timing Constraints Manager (Synopsys) or TimeVision (Ausdia) • Proven track record of executing STA on complex Macro-level designs and supporting Full-Chip timing integration • Strong background in scripting (Tcl, Python, Perl) and automation to enhance timing closure efficiency We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Staff DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters. As a Staff DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools—you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity. Key Responsibilities • DFT Architecture & Strategy • Own the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support • Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards • ​DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG methodologies • Test Pattern Development & Optimization • Generate and optimize high-quality test and debug patterns for production • Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance • Drive test coverage and quality metrics to meet stringent manufacturing requirements • Cross-Functional Collaboration & Methodology Innovation • Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR • Participate in developing and maintaining cutting-edge DFT implementation flows • Automate and improve methodologies using advanced scripting and tools Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 8+ years of hands-on experience in DFT roles at semiconductor companies • Deep expertise in DFT flows and architectures including JTAG/iJTAG, MBIST, Scan, and ATPG • Proficiency with industry-standard EDA tools from Synopsys (TestMAX) or Mentor (Tessent) • Strong understanding of logic design, verification, debug, and Static Timing Analysis (STA) • Scripting proficiency in Tcl, Perl, Python, or Shell for automation and innovation Preferred Qualifications • Master's degree in Electrical Engineering or related field • Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) and their specific test requirements • Experience in chip bring-up and mass production activities • Background in advanced process technologies (7nm and below) • Excellent communication skills with ability to work effectively in global team environments We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Staff/ Principal Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly. As a Staff/ Principal Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity. Key Responsibilities • Verification Environment Development • Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks • Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing • Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified • Coverage & Quality Assurance • Implement functional coverage models and analyze results to identify gaps in the verification process • Drive designs toward 100% verification closure through comprehensive test development • Contribute to verification methodology improvements and best practices • Debug & Cross-Functional Collaboration • Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle • Apply analytical skills and debugging techniques to solve intricate verification challenges • Collaborate effectively in a fast-paced, team-oriented R&D environment Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 5+ years of proven experience in ASIC verification within the semiconductor industry • Hands-on experience developing components within complex verification environments using SystemVerilog • Strong working knowledge of standard verification methodologies, specifically UVM • Sharp analytical mind with passion for debugging and technical problem-solving • Excellent communication skills with ability to thrive in collaborative R&D environments Preferred Qualifications • Master's degree in Electrical Engineering or related field • Familiarity with Formal Verification or Emulation flows • Basic proficiency in scripting languages such as Python or Tcl to automate verification tasks • Exposure to industry-standard protocols such as AMBA, PCIe, Ethernet, or CXL • Experience with assertion-based verification and constrained-random testing • Background in connectivity or networking silicon verification We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is a hyper-growth connectivity company building the purpose-built silicon that powers rack-scale AI infrastructure. As a Principal Physical Design Engineer and Team Lead in Israel, you will lead physical design teams that take complex, high-speed mixed-signal and digital SoCs from RTL handoff through tapeout. You will set the technical direction, drive execution across multiple projects, and grow the engineers around you, partnering closely with RTL, DFT, analog, and architecture teams. Your work will directly shape the performance, power, and area of products that connect the world's most demanding AI platforms. Key Responsibilities • Technical Leadership and Team Execution • Lead and mentor physical design engineers, setting priorities, assigning work, and ensuring high-quality, on-time delivery • Drive physical design projects end to end, including planning, scheduling, risk management, and status reporting • Define and evolve physical design methodologies, flows, and best practices across the team • Physical Implementation • Own block-level and top-level implementation: floorplanning, placement, clock tree synthesis, routing, and optimization • Drive timing closure, power integrity, and signal integrity to meet aggressive PPA targets in advanced process nodes • Lead physical verification and sign-off activities, including STA, IR/EM, DRC, LVS, and ECO management • Cross-Functional Collaboration • Partner with RTL design, DFT, analog, and architecture teams to resolve cross-domain implementation challenges early • Work with foundry, EDA vendors, and IP providers to ensure smooth tapeout and silicon bring-up • Contribute to hiring, onboarding, and professional development of team members Basic Qualifications • 10+ years of hands-on experience in physical design of complex SoCs or ASICs • Proven experience leading projects and technical teams through one or more full-chip tapeouts • Deep expertise with industry-standard physical design and sign-off tools (e.g., Cadence Innovus, Synopsys Fusion Compiler/ICC2, PrimeTime, Calibre) • Strong knowledge of timing closure, power/clock distribution, and physical verification in advanced process nodes • Excellent communication skills and the ability to work in a fully in-person, collaborative environment Preferred Qualifications • Experience with high-speed interface designs such as PCIe, Ethernet, or SerDes-based products • Proficiency in scripting languages such as Tcl, Python, or Perl for flow automation • Experience with hierarchical design, low-power methodologies, and ECO-driven closure • Demonstrated ability to mentor engineers and drive continuous improvement in team processes We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

SciPlay is a leading developer and publisher of digital games on mobile and web platforms, providing highly entertaining free-to-play games that millions of people play every day for their authenticity, engagement and fun. SciPlay currently offers nine core games, including social casino games Jackpot Party Casino, Gold Fish Casino Slots, Hot Shot Casino and Quick Hit Slots, and casual games MONOPOLY Slots, Bingo Showdown, 88 Fortunes Slots, Backgammon Live and Solitaire Pet Adventure with offices all over the world! Position Summary Serve as the Head of Engineering for 88 Fortunes, leading the engineering organization responsible for the game’s Unity client and backend services. As a member of the 88 Fortunes studio leadership team, this role also contributes to the studio’s broader strategic direction and priorities. This role combines people leadership, technical direction, delivery ownership, and hands-on architectural judgment across the full product stack. Key Responsibilities : • Own the engineering strategy, execution, and technical roadmap for 88 Fortunes across client and backend development. • Lead, coach, and grow engineering managers and senior engineers, building a high-performing and accountable organization. • Create clear ownership, operating rhythms, engineering standards, and measurable goals across teams. • Partner closely with Product, Design, QA, Analytics, Live Operations, DevOps, and other stakeholders to translate business priorities into reliable delivery plans. • Drive predictable execution, release quality, technical risk management, and continuous improvement across the software development lifecycle. • Balance feature delivery with platform health, architecture evolution, scalability, security, observability, and reduction of technical debt. • Own hiring, workforce planning, succession planning, and development of engineering talent. • Establish and track engineering metrics covering delivery, quality, reliability, operational health, and team effectiveness. • Communicate technical direction, tradeoffs, risks, and progress clearly to senior leadership and non-technical stakeholders. Requirements: • Extensive software engineering experience, including significant leadership of multiple teams or an engineering organization. • Proven experience delivering complex, customer-facing products that include both client applications and backend services. • Strong technical depth in at least one side of the stack, with demonstrated ability to lead architecture and make sound decisions across both client and backend domains. • Experience leading Unity client development or closely related real-time, mobile, or game-client technologies. • Strong backend engineering experience with APIs, distributed systems, databases, cloud infrastructure, scalability, reliability, and production operations. • Experience hiring, coaching, and developing managers, technical leaders, and senior individual contributors. • Ability to combine strategic thinking with pragmatic execution and to make clear tradeoffs among scope, quality, speed, and technical sustainability. • Excellent written and verbal communication skills, including the ability to influence across functions and at executive level. Client Engineering Leadership (Unity): • Provide technical and organizational leadership for Unity-based client development. • Guide architecture and engineering practices for maintainable, modular, performant, and testable client systems. • Ensure strong practices for memory and performance optimization, asset management, build pipelines, release management, and platform compatibility. • Drive high-quality player experiences through close collaboration with product, design, art, QA, and backend teams. • Oversee client stability, crash reduction, diagnostics, telemetry, and production issue resolution. Backend Engineering Leadership: • Lead the design and operation of scalable, reliable, secure, and observable backend services and APIs. • Guide architecture for distributed systems, data flows, integrations, service ownership, and production operations. • Promote strong engineering practices in automated testing, CI/CD, monitoring, incident response, performance, and capacity planning. • Ensure effective collaboration between client and backend teams on API contracts, versioning, data consistency, feature rollout, and backward compatibility. • Our current backend is primarily PHP. Deep PHP expertise is preferred but not required; strong senior-level backend experience in comparable production environments is acceptable, with the ability and willingness to work effectively in a PHP ecosystem.

SciPlay is a leading developer and publisher of digital games on mobile and web platforms, providing highly entertaining free-to-play games that millions of people play every day for their authenticity, engagement and fun. SciPlay currently offers nine core games, including social casino games Jackpot Party Casino, Gold Fish Casino Slots, Hot Shot Casino and Quick Hit Slots, and casual games MONOPOLY Slots, Bingo Showdown, 88 Fortunes Slots, Backgammon Live and Solitaire Pet Adventure with offices all over the world! Position Summary We are looking for a General Manager to lead Quick Hit Slots, one of SciPlay's social casino games, with full ownership of its performance, product strategy and long-term growth. You will oversee the full game lifecycle (product, development, resources and communication) as part of the game management team, shaping vision, strategy and culture while leading, mentoring and growing a team of talented leaders. The role combines business ownership, product leadership, data-driven decision-making and the use of AI tools to improve efficiency, accelerate execution and find new growth opportunities. Key Responsibilities • Provide a clear, transparent product vision and own the roadmap, aligned with business objectives, player needs and long-term growth. • Make final decisions on release scope, bug fixes and feature direction. • Be accountable for game identity, game design strategy, monetization strategy and execution. • Drive performance, engagement, retention and monetization through data-driven strategies and continuous optimization. • Work with executives to secure alignment and buy-in from key stakeholders on product direction. • Ensure strong talent at lead and director levels; partner with department heads on performance reviews and talent development. • Maintain and foster a positive culture aligned with SciPlay values. • Define the project's organizational structure, including team structure and resource allocation. • Own the game's P&L and drive sustainable growth aligned with company goals. • Advocate for innovation, continuous improvement and positive organizational change. • Champion AI-powered tools across product development, analytics and operational workflows to improve productivity, decision-making and innovation. • Mentor, develop and lead high-performing teams and leaders. Requirements • Proven experience as a General Manager, Studio Manager, Studio Leader or equivalent leadership role. • Proven track record managing large-scale, cross-functional teams. • Strong experience in social casino or free-to-play mobile games, with deep understanding of engagement, retention and monetization. • Strong product or production background. • Solid understanding of data, business performance and marketing metrics. • Deep understanding of free-to-play monetization models, game economies, LiveOps and player lifecycle management. • Hands-on experience using AI tools to improve workflows, support decision-making and drive efficiency and innovation. • Strong critical thinking, strategic mindset and creative problem-solving skills. • Proven ability to lead multiple projects and priorities simultaneously. • Demonstrated ability to own and manage a P&L.

SciPlay is a leading developer and publisher of digital games on mobile and web platforms, providing highly entertaining free-to-play games that millions of people play every day for their authenticity, engagement and fun. SciPlay currently offers nine core games, including social casino games Jackpot Party Casino, Gold Fish Casino Slots, Hot Shot Casino and Quick Hit Slots, and casual games MONOPOLY Slots, Bingo Showdown, 88 Fortunes Slots, Backgammon Live and Solitaire Pet Adventure with offices all over the world! Position Summary We are looking for a Senior Platform Engineer with strong product thinking and a passion for developer experience. In this role, you will design and build software services as well as the platform they run on, working across infrastructure, backend services, and tooling to support our game devs. You will collaborate with multiple teams to identify friction points, improve workflows, and deliver scalable, reliable solutions. This position requires a hands-on engineer who can balance quick wins with long-term improvements, take ownership, and drive impact across the organization. Key Responsibilities: • Build self-service workflows and golden paths that let game teams provision environments, deploy, and troubleshoot independently, backed by clean APIs and maintainable code. • Design, build, and maintain internal developer platform capabilities (CI/CD, environments, observability, infrastructure). • Make architectural and design trade-offs for the services you build, including API contracts, data models, and testing strategy, not just the infrastructure they run on. • Identify and resolve developer pain points through data, feedback, and hands-on investigation. • Promote engineering excellence, including reliability, automation, and maintainability. • Collaborate with cross-functional teams to gather requirements and drive improvements. • Own operational aspects of systems, including monitoring, SLIs/SLOs, and on-call participation. • Contribute to architectural decisions and long-term platform strategy. Requirements: • 5–10+ years of software engineering experience (platform, infrastructure, or DevOps focus). • Strong product mindset with a passion for improving developer experience. • Strong software engineering fundamentals, demonstrated by designing, implementing, and maintaining production services in at least one of C#, Go, Python, or TypeScript, not just scripts and glue code. • Experience building and operating distributed systems on AWS in containerized environments (Docker, Kubernetes). • Strong problem-solving, communication, and collaboration skills. Nice to Have: • Experience working with game development teams. • Background in internal developer platforms or large-scale tooling. • Knowledge of security, compliance, or platform governance.

SciPlay is a leading developer and publisher of digital games on mobile and web platforms, providing highly entertaining free-to-play games that millions of people play every day for their authenticity, engagement and fun. SciPlay currently offers nine core games, including social casino games Jackpot Party Casino, Gold Fish Casino Slots, Hot Shot Casino and Quick Hit Slots, and casual games MONOPOLY Slots, Bingo Showdown, 88 Fortunes Slots, Backgammon Live and Solitaire Pet Adventure with offices all over the world! Position Summary We are looking for a motivated and proactive Talent Acquisition Partner to join our HR team on a maternity leave cover basis. This is an exciting opportunity to manage recruitment for local and global roles, partner with hiring managers across different markets and contribute to innovative and challenging talent acquisition initiatives. The ideal candidate is a strategic thinker with strong interpersonal skills, high ownership and a genuine passion for people and recruitment. They will bring fresh ideas, embrace new technologies and use AI-powered tools to improve the hiring process and candidate experience. Key Responsibilities • Manage assigned recruitment processes, including hiring manager kickoffs, day-to-day process management and reference checks. • Recruit for local and global roles across different markets and time zones. • Partner closely with hiring managers and HR stakeholders. • Source candidates using LinkedIn Recruiter, sourcing platforms and creative recruiting methods. • Build and maintain strong talent pipelines. • Use Applicant Tracking Systems, HR technologies and AI tools to support effective recruitment. • Provide a positive and engaging candidate experience. • Support process improvements and contribute to strategic talent acquisition projects. Requirements • 2 years of experience in Talent Acquisition or Recruitment. • Experience managing and coordinating recruitment processes in partnership with hiring managers. • Experience recruiting for global or international roles is an advantage. • Strong communication, stakeholder management and interpersonal skills. • Strategic, organized and able to manage multiple priorities and deadlines. • Proactive, adaptable and eager to learn and introduce new ideas. • Genuine motivation to work in a dynamic and evolving recruitment environment. • Excellent written and verbal communication skills in English and Hebrew.

SciPlay is a leading developer and publisher of digital games on mobile and web platforms, providing highly entertaining free-to-play games that millions of people play every day for their authenticity, engagement and fun. SciPlay currently offers nine core games, including social casino games Jackpot Party Casino, Gold Fish Casino Slots, Hot Shot Casino and Quick Hit Slots, and casual games MONOPOLY Slots, Bingo Showdown, 88 Fortunes Slots, Backgammon Live and Solitaire Pet Adventure with offices all over the world! Position Summary SciPlay is looking for a new role in a Head of Production which will be responsible for its industry leading Monopoly Slots Casino game. Experience driving and communicating a clear vision in a highly collaborative environment, managing and mentoring production, and being a true partner to Art, Design, Engineering, Production, and Quality Assurance is essential. Key Responsibilities • Support GM and studio management to drive production initiatives, whether it’s product quality, tech stack, platform integration, feature roadmaps, marketing collaborations or analytics needs. • Manage master production plan. Scope and plan feature level tasks, schedules, and task cross discipline teams to execute on time and at high quality. • You drive the team to get results and you do so through establishing or maintaining a culture of commitment, accountability, and predictability. • You set production goals for your team around performance and quality. You then measure the effectiveness of your team and identify inefficiencies. Based on this analysis, you perform root cause analysis, and other techniques to identify the appropriate corrective actions. • You are passionate about project management, pulling from multiple development methodologies, and coaching the production team when to use or adapt each one based on the problems the team is trying to solve. • Assist design and product teams to create short-term and long-term live operation plans, including feature and patch release cadences, as well as resource allocations and production processes for efficient quality live services. • Keep pulse on team morale and personnel issues. Actively work with leadership team to engage and create positive and inclusive team culture. • Identify areas for improvement with production tooling and reporting to assist with monitoring the effectiveness of the team. Keep abreast with the latest software technology to help the team drive forward. • Manage short-term and long-term resource and budget plan by working with GM and Finance. Requirements • 5+ years' experience in leading mobile game production pipeline with shipped titles. • Experienced in managing production pipeline throughout mobile game lifecycle including live operations. • Experienced in co-development relationship with oversea partners. • Experienced in working with supporting and service teams such as marketing, legal, finance, creative, HR etc. • Excellent leadership, project management, oral and written communication skills. • Effective verbal and written communication skills. • Solid organizational skills and highly efficient time management. • Keen knowledge of mobile, PC and platform development pipelines as they relate to games and game production. • Proficient in people management skills to motivate and grow the team. • Strong knowledge of the mobile game market and platforms. • International game or business experience. Key Attributes • Strong capability to multitask and prioritize. • Unrelenting self-motivation and initiative – comfortable with ambiguity but driven to create structure and order. • Absolute passion for playing and making games.

Corporate: Light & Wonder’s corporate team is comprised of incredible talent that works across the enterprise, defying boundaries to provide essential services in an extraordinary manner to ensure the success of the organization and the well-being of employees. Position Summary SciPlay is a leading developer and publisher of free-to-play digital games for mobile and web platforms, entertaining millions of players around the world every day. We are looking for a Junior IT Support with a service mindset, curiosity, and strong technological orientation. You will provide front-line technical support to end users across hardware, software, and access issues, resolving requests within SLAs and offering remote or hands-on help. The role includes adopting company-specific platforms, including AI-enabled tools that improve support and productivity. Key Responsibilities: • Provide 1st level remote or on-site IT support as the link between the IT department and users. • Support Windows, Ubuntu/Linux, and macOS computers, printers, mobile devices, and peripherals. • Install, configure, and maintain end-user devices, including imaging, patching, and software deployment. • Handle user account, access, and permission requests according to security and ITSM procedures. • Maintain meeting rooms, audio/visual equipment, and collaboration technologies. • Work with System and Network Administrators to support local office infrastructure. • Manage the IT asset database, hardware inventory, and device lifecycle. • Onboard new employees, including device setup and tool orientation. • Write and maintain technical procedures, knowledge articles, and FAQs. • Follow ITSM processes: Incident, Request, Problem, Knowledge, Configuration, and Change Management. • Undertake project work independently and report progress back to stakeholders. • Use approved AI and automation tools responsibly to improve troubleshooting, documentation, and productivity, while protecting company data. • Identify opportunities to improve IT support through automation and modern tools. Requirements: • Experience in 1st level end-user IT support. • Hands-on experience with Windows and macOS. • Working knowledge of ITSM processes and ticketing systems. • Strong problem-solving, communication, and customer-service skills. • Fluent English and Hebrew. • Military experience, a technical course, or relevant studies are an advantage. Nice to Have: • Experience with device management and imaging tools. • Familiarity with scripting or automation. • Experience with AI-enabled tools. Qualifications