Jobs in Tel Aviv-Yafo

About Irregular Irregular is the first frontier security lab with the mission of protecting the world in the time of increasingly capable and sophisticated AI systems. We build next-generation defenses through high-fidelity research platforms that simulate and monitor real-world AI security scenarios. As AI systems become more powerful, we focus on staying ahead of emerging threats and vulnerabilities, ensuring these transformative technologies can be deployed safely and securely. About the Role As a Senior FullStack Engineer, you’ll join our engineering team and help build the next generation of Irregular’s products as they evolve into intuitive, polished, and powerful experiences for some of the most sophisticated AI organizations in the world. This is a highly impactful role for an engineer with strong frontend expertise who cares deeply about product quality and user experience, and can both build scalable systems and help lead the technical direction of the frontend. You’ll work closely with exceptional engineers, researchers, and founders to turn deeply technical capabilities into user-facing products that are clear, elegant, and highly effective. Representative Responsibilities: • Build and own full-stack product features end-to-end • Help shape the next generation of the company’s products • Lead the technical direction of the frontend architecture, development standards, and engineering culture • Build polished, high-quality user experiences for highly technical users • Collaborate closely with engineers, founders, and product stakeholders on product and technical decisions • Take ownership of projects from idea to production with high autonomy and impact What we're looking for: • Strong full-stack engineering experience with deep frontend capabilities • Hands-on frontend experience with React/Angular/TypeScript and modern frontend frameworks • Backend development experience with scalable production systems • Ability to work independently and lead projects from idea to production • Strong product intuition and passion for building exceptional user experiences • Comfort working closely with designers and building polished, pixel-perfect UIs across devices and screen sizes • Commitment to code quality, maintainability, and testing as part of the development process

About Irregular Irregular is the first frontier security lab with the mission of protecting the world in the time of increasingly capable and sophisticated AI systems. We build next-generation defenses through high-fidelity research platforms that simulate and monitor real-world AI security scenarios. As AI systems become more powerful, we focus on staying ahead of emerging threats and vulnerabilities, ensuring these transformative technologies can be deployed safely and securely. About the Role As a Software Engineer at Irregular, you will take ownership of designing, building, and scaling the production systems that power our evaluation and security platform for frontier AI models. Your work will focus on creating robust, resilient, and high-performance infrastructure—whether that’s distributed pipelines, backend services, or tooling that supports our research teams. This role is engineering-first with a strong research and cyber component. You will develop systems that must run reliably in production, integrate with external partners, and support large-scale data, experiments, and automated evaluations. You’ll drive architectural decisions, lead technical implementations, and shape how our platform evolves. Representative Responsibilities: • Architecting and scaling production-grade systems and workflows. • Building backend services, APIs, and monitoring tools for large-scale model evaluations. • Designing infrastructure that supports research experiments at scale. • Implementing agent frameworks in production environments • Designing and building challenges that measure a model’s ability to evade discovery, allowing us to see if models can operate on remote systems while avoiding detection by common defensive security tools. You may be a good fit if you: • Have strong software engineering fundamentals and multiple years of production experience. • Have experience working in multidisciplinary teams, and can adapt to rapidly evolving challenges. • Enjoy working at the intersection of engineering and applied research. • Are interested in AI and cybersecurity (experience in machine learning or cybersecurity is a plus but not necessary). • Care about the societal impacts of your work.

About Irregular Irregular is the first frontier security lab with the mission of protecting the world in the time of increasingly capable and sophisticated AI systems. We build next-generation defenses through high-fidelity research platforms that simulate and monitor real-world AI security scenarios. As AI systems become more powerful, we focus on staying ahead of emerging threats and vulnerabilities, ensuring these transformative technologies can be deployed safely and securely. About the Role As an AI researcher at Irregular, you'll be at the forefront of researching advanced frontier model capabilities and agent behavior, and help shape the future of AI security evaluation and mitigation. In this role, you will advance the frontier knowledge of AI and agentic frameworks, methods of assessing their ability, and mitigations for dangerous capabilities. Representative projects: • Researching capability elicitation methods to enhance model performance in evaluations. • Researching methodologies to assess generalization and coverage in model capabilities evaluation frameworks. • Contributing to academic publications and delivering research findings to customers. • Creating unique solutions to mitigate scenarios of AI loss of control or misalignment. • Advising and supporting the development of the products we’re building. You may be a good fit if you: • Have a strong research experience in machine learning, particularly with frontier AI models. • Can design and implement novel research approaches for emerging AI challenges. • Work well in a multidisciplinary team and can adapt to rapidly evolving research questions. • Have a track record of publishing peer-reviewed research in top-tier venues (e.g., AAAI, ACL, EMNLP, ICLR, ICML, Nature, NeurIPS, Science, or similar). • Care about the societal impacts of your work.

About Irregular Irregular is the first frontier security lab with the mission of protecting the world in the time of increasingly capable and sophisticated AI systems. We build next-generation defenses through high-fidelity research platforms that simulate and monitor real-world AI security scenarios. As AI systems become more powerful, we focus on staying ahead of emerging threats and vulnerabilities, ensuring these transformative technologies can be deployed safely and securely. About the Role As a cyber researcher at Irregular, you will be at the forefront of research on AI security. You will engage with questions such as how to protect the weights of an advanced model against cyber threats, and how to evaluate cyber capabilities such as AI’s ability to exploit vulnerabilities, carry out network attacks, and develop malware. This role sits at a unique intersection of cybersecurity expertise and AI capabilities, where your background in vulnerability and security research will help shape the future of AI security. Representative projects: • Expanding the quantity, quality, and variety of our cyber capabilities evaluation challenges (e.g. constructing original CTF-style vulnerability & exploitation challenges, network attack simulation challenges, and more, including original types of challenges). • Leading research into methods to mitigate cybersecurity risks related to the misuse of AI, the theft of model weights, or risks associated with integrating models with dangerous capabilities in AI agents. • Publishing your research and/or delivering research to our customers. • Advising and supporting the development of the products we’re building. Representative research questions about AI frontier models: • Can an AI find and exploit 0-days? • What’s the best way to measure a CTF challenge's difficulty level vs. an AI player's skill level? • Can an AI elevate an average computer science student’s cyber capabilities to that of a nation-state? You may be a good fit if you: • Have a strong background in vulnerability/security research & development such as having found vulnerabilities/CVEs, analyzed malware, researched detection methods for attacks, developed pentesting products or other attack tools, participated in CTF competitions or authored CTF challenges, or participated in other types of security research & development. • Work well in a multidisciplinary team and can adapt to rapidly evolving challenges. • Care about the societal impacts of your work.

About Irregular Irregular is the first frontier security lab with the mission of protecting the world in the time of increasingly capable and sophisticated AI systems. We build next-generation defenses through high-fidelity research platforms that simulate and monitor real-world AI security scenarios. As AI systems become more powerful, we focus on staying ahead of emerging threats and vulnerabilities, ensuring these transformative technologies can be deployed safely and securely. About the Role As a research engineer at Irregular, you'll be at the forefront of building systems to evaluate and secure frontier AI models. You'll work on infrastructure and experiments to assess model capabilities, implement agent frameworks, and develop mitigations for advanced AI systems. Your role will involve creating robust evaluation pipelines, developing security-focused testing frameworks, and building tools that help understand and mitigate risks related to frontier models. You’ll have a chance to understand the research context and your code’s impact and contribute as a meaningful part of a growing team. Representative projects: • Building a tool to continuously evaluate models and mitigate their risks. From designing the APIs for frontier labs, to building analysis and visualization tools that summarize 10,000+ transcripts into specific conclusions. • Designing and building challenges that measure a model’s ability to evade discovery, allowing us to see if models can operate on remote systems while avoiding detection by common defensive security tools. • Developing controlled environment frameworks for more secure use of frontier models. • Designing and building agents that improve a model’s ability to complete complex tasks. Includes many potential avenues, such as incorporating SOTA prompting practices, creating tools for task delegation, and more. • Publishing your research and/or delivering research to our customers. You may be a good fit if you: • Have strong production programming skills and experience. • Have strong problem-solving and analytical skills. • Work well in a multidisciplinary team and can adapt to rapidly evolving challenges. • Are interested in AI and cybersecurity (experience in machine learning or cybersecurity is a plus but not necessary). • Care about the societal impacts of your work.

About Irregular IIrregular is the first frontier security lab with the mission of protecting the world in the time of increasingly capable and sophisticated AI systems. We build next-generation defenses through high-fidelity research platforms that simulate and monitor real-world AI security scenarios. As AI systems become more powerful, we focus on staying ahead of emerging threats and vulnerabilities, ensuring these transformative technologies can be deployed safely and securely. About the Role We’re looking for a highly organized, proactive, and discreet Personal Assistant to support Irregular’s CTO and Co-Founder across his personal and professional life. This is a hands-on role with a high degree of ownership and autonomy. Approximately 70% of the role focuses on personal matters, household and family coordination, travel, and day-to-day logistics. The remaining 30% involves calendar management and professional and administrative support. You’ll anticipate needs, manage competing priorities, and make sure things get done, from everyday errands to complex arrangements. The role requires sound judgment, absolute discretion, and flexibility to respond outside standard working hours when needed. Key Responsibilities Personal Support (~70%) • Manage personal matters and errands end-to-end, including appointments, transportation, special projects, and ad hoc requests. • Coordinate household operations, service providers, and vendors, ensuring reliable execution and follow-through. • Manage family logistics and children’s schedules, including school administration, after-school activities, and appointments. • Plan and coordinate personal and business travel, including flights, accommodation, transportation, visas, and detailed itineraries. Handle changes and unexpected issues as they arise. • Organize personal events and activities, taking ownership of planning, coordination, and execution. Professional Support (~30%) • Own the CTO’s work and personal calendars, anticipating scheduling conflicts, managing priorities, and protecting time for focused work. • Coordinate internal meetings across the company and external meetings with partners, clients, and other stakeholders. • Manage expense reports, invoices, and billing for personal and professional matters, working with the Operations team where relevant. Requirements • 2+ years of experience as a Personal Assistant, Executive Assistant, or in a similar role in a fast-paced environment, ideally supporting senior executives. • Exceptional organizational skills and attention to detail, with reliable follow-through across multiple tasks and deadlines. • Ability to take ownership, anticipate needs, and solve problems independently with minimal guidance. • Sound judgment and absolute discretion when handling sensitive personal, family, and business information. • Strong interpersonal and communication skills, with the ability to build trusted relationships with family members, colleagues, service providers, and vendors. • Ability to stay calm, adapt quickly, and prioritize effectively as plans and needs change. • Fluent Hebrew and English, both written and spoken. • Willingness to handle personal errands and household logistics hands-on, and availability outside standard working hours when required. Nice to Have • Experience using AI tools and productivity apps to streamline planning, coordination, and administrative work. • Experience working in a startup or technology company.

About Irregular Irregular is the first frontier security lab with the mission of protecting the world in the time of increasingly capable and sophisticated AI systems. We build next-generation defenses through high-fidelity research platforms that simulate and monitor real-world AI security scenarios. As AI systems become more powerful, we focus on staying ahead of emerging threats and vulnerabilities, ensuring these transformative technologies can be deployed safely and securely. About the Role As Irregular’s Senior DevOps Engineer, you will play a critical role in shaping our infrastructure, deployment pipelines, and operational foundations. This is a hands-on, high-ownership role with real influence over how the company builds, deploys, and operates its systems in production. You’ll be building infrastructure that supports work with frontier AI labs such as Google, Anthropic, and OpenAI, and meets the scale, security, and reliability standards this ecosystem requires. This includes architecting ephemeral, on-demand environments, and spinning up and tearing down multi-service deployments (VPCs, compute, serverless components, and more) as needed. You will work closely with research, engineering, security, and leadership to design and maintain scalable infrastructure, improve system reliability, and enable fast, safe, and secure product delivery. Key Responsibilities • Own and evolve Irregular’s cloud infrastructure, with a strong focus on scalability, security, and reliability • Design, build, and maintain end-to-end CI/CD pipelines and deployment workflows • Lead and continuously improve containerized environments (Docker, Kubernetes) • Build and maintain Infrastructure as Code and automation frameworks (e.g., Terraform) • Own production readiness: availability, monitoring, logging, alerting, and incident response • Work closely with engineering and research teams to support development, testing, and production needs • Drive improvements in system performance, reliability, and security posture • Take part in - and often lead architectural decisions and long-term infrastructure planning • Act as a key operational owner in a fast-growing startup, setting best practices and standards Requirements • 5+ years of hands-on experience as a DevOps / Infrastructure Engineer in production environments • Strong, hands-on experience with AWS (architecture, networking, security, and cost awareness) • Proven experience with containerization and orchestration (Docker, Kubernetes) in production • Hands-on experience designing and maintaining CI/CD pipelines (e.g., GitHub Actions or similar) • Strong experience with Infrastructure as Code and automation (e.g., Terraform) • Ability to take end-to-end ownership and operate independently in an early-stage, high-ambiguity environment Nice to Have • Experience working closely with research or security teams in production environments • Background supporting data-heavy, distributed, or high-scale systems • Familiarity with monitoring, observability, and alerting tools (e.g., Prometheus, Grafana, Datadog)

About Irregular Irregular is the first frontier security lab with the mission of protecting the world in the time of increasingly capable and sophisticated AI systems. We build next-generation defenses through high-fidelity research platforms that simulate and monitor real-world AI security scenarios. As AI systems become more powerful, we focus on staying ahead of emerging threats and vulnerabilities, ensuring these transformative technologies can be deployed safely and securely. About the role Our Operations team works across the business, supporting everything from commercial and marketing initiatives to finance, internal systems and employee experience. Reporting to the Head of Operations, you’ll take ownership of projects, build processes where they’re needed, and help teams get things done. This is a hands-on role for someone who enjoys variety, learns quickly and can turn an unfamiliar challenge into a clear plan and a completed project. What you’ll do • Lead projects across the company: Own operational initiatives from defining the need through execution, coordinating stakeholders, budgets and timelines. • Support business and commercial operations: Partner with business teams, Legal and Finance to coordinate customer onboarding, procurement requirements and other commercial processes. • Support marketing operations: Coordinate the execution of events, conferences, campaigns and launches, including agencies, vendors, materials, budgets and logistics. • Build processes and systems: Identify gaps, improve workflows and implement tools and automation that help teams work more effectively. • Manage vendors and purchasing: Own sourcing, negotiations, onboarding, renewals and ongoing service management across company needs. • Support financial operations: Manage purchasing and invoice workflows, track spending against budgets, and identify opportunities to improve efficiency and reduce costs. • Coordinate company infrastructure: Work with IT and security providers on equipment, access, service delivery and operational projects. • Support people and workplace operations: Partner with HR on onboarding, offboarding and employee initiatives, and help manage office needs as the company grows. • Take on emerging priorities: Research options, recommend solutions and independently drive new initiatives as business needs evolve. What you’ll bring • 4+ years of experience in operations, business operations or a similarly broad role, including hands-on experience at a startup - a must. • A track record of delivering projects involving multiple teams and managing several priorities simultaneously. • Experience building or improving processes, rather than only following established ones. • Strong organizational skills, attention to detail and reliable follow-through. • Good business judgment, confidence working independently and the ability to recognize when to escalate. • Comfort with budgets, spreadsheets and operational data. • Experience managing vendors and working with internal stakeholders and external partners. • Confidence in learning new systems and using AI and automation tools in your work. • Excellent Hebrew and English, written and spoken. • A practical, collaborative approach and equal willingness to lead a project or handle the details needed to complete it. An advantage: Experience supporting marketing or commercial operations, familiarity with CRM and project management tools, or experience in AI or cybersecurity.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity. Key Responsibilities • Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments • Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence • Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments • Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners • Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient Basic Qualifications • B.Sc. in Electrical Engineering or Computer Engineering • 6+ years of hands-on experience in Static Timing Analysis (STA) at semiconductor companies, specifically working on advanced process technologies. (Note: Adjust years of experience based on the exact level you are targeting) • Deep expertise in multi-scenario STA, as well as timing and SDC constraint development and verification at the block and subsystem levels • Solid understanding of advanced margining methodologies, including OCV, AOCV, and POCV, from synthesis through to final sign-off • Solid knowledge of physical design flows (Synthesis, P&R, Physical Verification) and how they intersect with timing closure Preferred Experience • Experience developing and validating constraints using industry-standard tools like Timing Constraints Manager (Synopsys) or TimeVision (Ausdia) • Proven track record of executing STA on complex Macro-level designs and supporting Full-Chip timing integration • Strong background in scripting (Tcl, Python, Perl) and automation to enhance timing closure efficiency We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. The Role and Its Impact Our firmware team develops the embedded firmware that brings Astera Labs' compute connectivity silicon to life, from boot and initialization through link management, telemetry, error handling, and diagnostics. This firmware runs on the embedded processors inside our chips and ships in data centers powering AI infrastructure around the world. Beyond the firmware, the team also develops the COSMOS SDK, the software layer customers and internal teams use to configure, monitor, update, and debug our devices in their systems. We are looking for an experienced firmware engineer and PCIe expert who enjoys working close to the hardware, owns features end to end, and has a proven track record of developing and debugging firmware both pre-silicon and post-silicon. You know PCIe in depth, from link training and enumeration to error handling and recovery, and you're the person others turn to when a PCIe link or device misbehaves. You understand the whole system, not just the chip: how our devices behave inside customer platforms, and how a customer requirement turns into firmware and SDK. You'll work alongside architects, design and verification engineers, validation teams, and our global firmware teams to take new products from early pre-silicon development through bring-up and into customer deployment. What You'll Be Doing • Having fun! by being part of a very strong and cohesive group. • Design and develop real-time embedded firmware in C, including low-level drivers and control logic for complex hardware blocks • Own PCIe firmware features end to end: link training, enumeration, error handling, and recovery • Develop and debug firmware pre-silicon (emulation) and lead post-silicon bring-up and debug in the lab • Debug complex PCIe and system-level issues with architecture, design, validation, and customer teams • Develop and extend the company SDK in step with firmware features • Support customer requests and adjust firmware and SDK development to meet their needs What We're Looking For Required: • BSc/MSc in Computer Science, Electrical Engineering, Computer Engineering, or a related field • 10+ years of hands-on experience as a firmware engineer • Proven experience in embedded and real-time firmware development • Strong programming skills in C on resource-constrained, bare-metal, or RTOS-based systems • Solid understanding of processor architecture, memory-mapped registers, interrupts, and HW/SW interaction • Expert-level knowledge of PCIe: LTSSM and link training, enumeration, configuration space, error handling (AER), and reset and recovery flows • Experience with PCIe protocol analyzers and exercisers (e.g., Teledyne LeCroy, Keysight) • Proven hands-on experience in both pre-silicon and post-silicon firmware development and debugging, including silicon bring-up of new SoCs • Strong debugging skills on real hardware using JTAG debuggers, logs, and register-level analysis • Broad system-level understanding of how silicon, firmware, SDK, host software, and platform interact, with the ability to turn customer requirements into technical solutions • A team player with excellent communication skills who works well in a collaborative, cross-site environment • Comfort with ambiguity and ownership in a fast-moving, high-growth company Location This position is based in our Tel Aviv, Israel office. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. We are looking for a Post-Silicon Validation Engineer with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams. Key Responsibilities • Perform hands-on post-silicon validation • Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability. • Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements. • Drive complex issues from initial failure through root-cause analysis and final resolution. • Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries. • Validate PCIe functionality across different generations, platforms, configurations, and operating conditions. • Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests. • Develop automation to improve validation coverage, debug efficiency, and regression testing. Required Qualifications • BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience. • 5+ years of engineering experience in silicon validation, post-silicon debug, or high-speed interface development. • Strong hands-on knowledge of PCIe architecture and protocol. • Experience working with PCIe analyzers, state traces, registers, logs, eye diagrams, and/or signal-integrity measurements. • Strong problem-solving skills and ability to independently drive issues to root cause. • Experience working across hardware, firmware, and software boundaries. • Good scripting/programming skills, preferably Python • Good Linux knowledge and experience with Linux PCIe debug tools. • Strong communication and collaboration skills. Preferred Qualifications • Experience with PCIe Gen4/Gen5/Gen6/Gen7 • Hands-on experience with PCIe PHY, SerDes, equalization, lane margining, or signal integrity. • Experience with PCIe compliance and interoperability testing. • Experience debugging intermittent, marginal, thermal-sensitive, or corner-case PCIe failures. • Experience with PCIe switches, or networking/accelerator platforms. • Practical experience using AI/ML tools for engineering debug and automation. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Manager Design Verification Tel Aviv District, Israel Astera Labs is seeking an experienced Manager, Design Verification to lead a team responsible for verifying the next generation of connectivity silicon powering the world's largest AI clusters. In this role, you will drive verification strategy and execution for complex SoC and IP designs supporting PCIe, CXL, Ethernet, UALink, and other advanced interconnect technologies. You will partner closely with Architecture, Design, Firmware, Post-Silicon Validation, and Program Management teams to ensure first-pass silicon success while scaling methodologies and processes across a growing organization. Key Responsibilities Verification Leadership • Lead and mentor a team of Design Verification engineers. • Define verification strategies, schedules, and execution plans for IP, subsystem, and SoC-level verification. • Drive verification planning, resource allocation, and project execution to meet aggressive tapeout schedules. Verification Development & Execution • Own verification sign-off criteria, coverage metrics, and quality standards. • Develop and review UVM/SystemVerilog testbenches, checkers, scoreboards, and verification components. • Collaborate with Design and Architecture teams to ensure comprehensive verification of specifications and microarchitectures. Methodology & Quality • Establish and improve verification methodologies, infrastructure, and best practices. • Establish reusable verification frameworks across multiple projects. • Ensure high-quality metrics-driven verification sign-off. Cross-Functional Collaboration • Work closely with RTL Design, DFT, Firmware, Post-Silicon Validation, and Physical Design teams. • Support bring-up and debug activities by correlating pre-silicon and post-silicon results. • Contribute to technical roadmap discussions and verification planning for future products. Basic Qualifications • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field. • 8+ years of ASIC/SoC verification experience. • 4+ years of technical leadership or people management experience. • Strong expertise in SystemVerilog and UVM. • Experience creating complex verification environments from architecture through sign-off. • Familiarity with SoC architectures and high-speed interfaces. Preferred Qualifications • Experience verifying PCIe Gen5/Gen6, CXL, Ethernet, UCIe, UALink, or similar protocols. • Knowledge of advanced SoC architectures and coherent fabrics. • Proven track record of shipping complex silicon products successfully. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. We are seeking an experienced Principal Architect to lead the architecture of high-performance connectivity solutions, with a strong focus on PCIe, high-speed networking, and Ethernet-based systems. This role will define next-generation architectures for AI infrastructure, working at the intersection of silicon, system, and protocol design. You will play a key role in shaping innovative solutions that enable hyperscale customers to build scalable, high-bandwidth, and low-latency systems. This is a unique opportunity to join a new and growing Israel site, influence technical direction, and take ownership of critical architectural decisions impacting industry-leading products. Key Responsibilities • Define and drive system and chip-level architecture for high-speed connectivity products • Lead architecture for PCIe-based interconnects, networking protocols, and Ethernet subsystems • Analyze system requirements and translate them into scalable and efficient hardware architectures • Drive tradeoff analysis across performance, power, latency, area, and cost • Collaborate with cross-functional teams including RTL, Physical Design, Firmware, Validation, and Product Engineering • Define and review micro-architecture specifications and ensure alignment across teams • Contribute to standard-based and custom protocols for next-generation AI infrastructure • Support performance modeling, simulation, and architectural validation • Work closely with customers and partners to understand emerging use cases and requirements • Mentor engineers and help build strong technical leadership within the Israel R&D center Basic Qualifications • 10+ years of experience in semiconductor architecture, ASIC design, or system engineering • Strong expertise in PCIe architecture (Gen4/5/6+) and its ecosystem • Deep understanding of Networking and Ethernet (e.g., 25G/50G/100G/400G and beyond) • Experience designing high-speed, low-latency data paths • Solid understanding of SoC architecture and integration challenges • Experience working across full chip development lifecycle • Strong analytical and problem-solving skills with ability to evaluate complex tradeoffs • Ability to influence and collaborate across multiple engineering domains Preferred Experience • Experience with CXL, NVLink, UALink, or other advanced interconnect protocols • Background in AI/ML infrastructure, data center systems, or hyperscaler environments • Experience with SerDes-based systems and high-speed PHY integration • Familiarity with networking stacks, switching, or RDMA technologies • Experience with performance modeling tools and architectural simulators • Knowledge of power/performance optimization techniques at system level • Track record of driving architecture from concept to silicon We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Principal DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters. As a Principal DFT Engineer, you will provide technical leadership across the full DFT lifecycle—from architecture and specification through implementation, verification, and silicon bring-up. You will define and drive DFT strategy, establish robust methodologies, and lead execution to ensure high test quality and manufacturability. This role requires deep expertise, cross-functional influence, and the ability to drive DFT excellence across projects and teams. This is a critical leadership position with high impact on first-pass silicon success and production quality for next-generation AI connectivity solutions. Key Responsibilities DFT Architecture & Technical Leadership • Define and own DFT architecture for complex SoCs, including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG strategies • Lead DFT planning, specification, and quality tracking across the project lifecycle • Provide technical leadership and drive DFT sign-off readiness to ensure successful tapeout Execution Across the Full Lifecycle • Lead DFT implementation, integration, and verification at block, full-chip and chiplet levels • Own end-to-end DFT activities from specification through silicon bring-up and production support • Ensure high test coverage, robust pattern generation, and alignment with manufacturing requirements Methodology & Cross-Functional Impact • Develop and drive scalable DFT methodologies, flows, and automation frameworks • Collaborate closely with RTL, Physical Design, STA, and Test Engineering teams to ensure design-for-test readiness • Optimize DFT integration across front-end and backend flows to improve quality, PPA, and turnaround time Basic Qualifications • Bachelor’s degree in Electrical Engineering or related technical field (Master’s preferred) • 12+ years of experience in DFT design, implementation, and verification for complex ASIC/SoC designs • Proven experience in leading DFT activities across full chip development cycles • Deep expertise in DFT techniques including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG • Strong understanding of DFT and Physical Design flows, including timing implications and integration challenges • Experience with industry-standard DFT tools (Siemens Tessent, Synopsys TestMAX or equivalent) • Solid experience with DFT verification methodologies and coverage analysis • Strong scripting skills (Tcl, Python, or Perl) for automation and flow development Preferred Qualifications • Experience with advanced process nodes (7nm and below) • Background in high-speed connectivity designs (PCIe, Ethernet, CXL, or similar) • Experience with hierarchical DFT methodologies and large multi-die or chiplet-based systems • Knowledge of silicon bring-up, production test flows, and yield optimization • Familiarity with STA, low-power design, and CDC as it relates to DFT integration • Strong leadership and communication skills, with ability to influence cross-functional teams globally We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters. As a DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools—you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity. Key Responsibilities • DFT Architecture & Strategy • Be part of the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support • Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards • Design and implement DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG for high-end devices • Test Pattern Development & Optimization • Generate and optimize high-quality test and debug patterns for production • Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance • Drive test coverage and quality metrics to meet stringent manufacturing requirements • Cross-Functional Collaboration & Methodology Innovation • Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR • Participate in developing and maintaining cutting-edge DFT implementation flows • Automate and improve methodologies using advanced scripting and tools Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 4+ years of hands-on experience in DFT roles at semiconductor companies • Experience in DFT flows and architectures including JTAG/iJTAG, MBIST, Scan, and ATPG • Good understanding of logic design, verification, debug, and Static Timing Analysis (STA) • Scripting proficiency in Tcl, Perl, Python, or Shell for automation and innovation Preferred Qualifications • Master's degree in Electrical Engineering or related field • Experience with industry-standard EDA tools from Synopsys (TestMAX) or Siemens (Tessent) • Experience in chip bring-up and mass production activities • Background in advanced process technologies (7nm and below) • Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) and their specific test requirements • Excellent communication skills with ability to work effectively in global team environments We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Principal Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters. As an Principal Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity. Key Responsibilities • Emulation Flow Execution & Implementation • Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging • Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies • Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market • System-Level Debug & Validation • Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs • Ensure rapid cycles from RTL to functional stability through systematic debug approaches • Own technical blocks and drive them to completion independently • Cross-Functional Collaboration • Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios • Ensure seamless hardware-software integration for AI infrastructure connectivity • Collaborate with Design and Verification teams to optimize emulation strategies Basic Qualifications • Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field • 10+ years of hands-on experience in Emulation at semiconductor companies • Deep expertise in emulation flows for large-scale chips using industry-standard emulators (Zebu, Palladium, or Veloce) • Strong background in SystemVerilog for developing, testing, and debugging complex SoC designs • Experience developing and maintaining execution flows for building, running, and debugging emulation models • "Can-do" approach with ability to own technical blocks and drive them to completion independently Preferred Qualifications • Master's degree in Electrical Engineering, Computer Engineering, or related field • Familiarity with EDA tools for Lint, Clock Domain Crossing (CDC), simulation, and synthesis • Proficiency in scripting languages such as Python or TCL for automation and flow enhancement • Experience with standard debug environments (e.g., Verdi) • Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) • Background in hardware-software co-verification methodologies We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we are seeking a motivated Physical Design Student to join our founding local engineering team. This is a unique opportunity to kickstart your career in the semiconductor industry. Working alongside senior industry veterans, you will gain hands-on experience in backend execution and advanced methodologies for cutting-edge chips that power the world's largest AI clusters. If you are passionate about silicon hardware, eager to learn, and thrive on solving complex engineering challenges, this role offers the perfect bridge between your academic studies and a high-impact career. Key Responsibilities Guided Implementation & Learning • Partner with and learn from senior engineers to support the physical implementation journey, including synthesis, floorplanning, Place & Route (P&R), and Clock-Tree Synthesis (CTS) • Assist in macro-level implementation and develop hands-on skills in complex layout routing • Participate in deep-submicron process challenges under close professional mentorship Signoff & Design Integrity Support • Assist in running engineering checks for design integrity, including Static Timing Analysis (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR) • Learn to apply Logic Equivalence Checking (LEC) to help guarantee design correctness • Gain exposure to the rigorous flows required to ensure first-pass silicon success Scripting & Cross-Functional Collaboration • Leverage and develop scripting tools to automate repetitive tasks and optimize the engineering environment • Collaborate with Architecture, Design, and DFT teams to understand how different chip design disciplines intersect • Actively participate in team reviews and technical discussions to ramp up backend methodologies Basic Qualifications • Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field • Strong academic foundation in digital systems, VLSI design, or semiconductor devices. • Familiarity with Python, TCL, Bash, or Perl. • Ability to work at least 2 days per week at our Haifa/Tel Aviv Center • A "can-do" attitude with a passion for solving complex technical challenges • Fluent in Hebrew and English with the ability to work effectively in a team environment Preferred Qualifications • Prior experience from a previous VLSI/Hardware student position or a significant academic project in physical design/VLSI • Hands-on university lab experience with industry-standard EDA tools (e.g., Synopsys Fusion Compiler/ICC2, Cadence Innovus) • Understanding of basic verification concepts (STA, DRC, LVS) • Fast learner with a proactive attitude and a passion for deep-tech hardware infrastructure We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up. If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us. As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the world’s largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale. Key Responsibilities • Execute SoC Top-level physical design and actively drive full-chip convergence • Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff • Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR) • Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon • Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration Basic Qualifications • B.Sc. or M.Sc. in Electrical Engineering • 5+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below) • Proven experience executing complex block or chip-level projects with a proactive, "can-do" approach and excellent communication skills • Deep hands-on expertise in RTL2GDS flows, including P&R, STA, Physical Verification (DRC/LVS), Formal Verification, low-power implementation (UPF/CPF), and EMIR • Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2 or Cadence Innovus) • Practical experience handling both complex macro/subsystem-level designs and Full-Chip integration Preferred Qualifications • Deep understanding of Power & Noise analysis (EM/IR) • Experience with DFT (Design for Test) integration into the physical design flow • Background in high-speed interfaces or data center protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects. As a Senior ASIC Design Engineer, you won't just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity. Key Responsibilities • Design Ownership & Implementation • Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support • Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions • Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams • Quality Assurance & Design Optimization • Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient • Apply design techniques to meet PPA (Power, Performance, Area) targets • Contribute to design quality through verification and validation activities • Methodology Innovation & Collaboration • Participate in design methodology improvements and tool automation initiatives • Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter • Collaborate effectively across teams to ensure seamless integration Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 3+ years of experience in logic design at semiconductor companies • Knowledge and experience in Verilog and/or SystemVerilog • Excellent communication skills with ability to work effectively across teams • Understanding of digital design principles and RTL coding best practices Preferred Qualifications • Master's degree in Electrical Engineering or related field • Knowledge of DDR and PCIe protocols and implementation • Understanding of power management techniques for low-power design • Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis • Proficiency in scripting languages such as Python or Perl • Experience with high-speed serial interface designs or connectivity protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the world’s most demanding AI and cloud environments. Key Responsibilities • Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip • Collaborate closely with Physical Design team to insure a full power integrity • Partner with Package Design engineers to perform Chip-Package co-analysis (CPM) • Understand root-cause analysis for voltage drop violations and EM risks Basic Qualifications • Bachelor's or Master's degree in Electrical Engineering or a related technical field • 7+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products • Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, or Cadence Voltus) • Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm) • Deep understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture • Deep understanding of EM and trade-offs between signal EM and power grid (PG) EM Preferred Experience • Familiarity with thermal analysis tools and their interaction with electrical performance • Experience working with sign-off criteria and margins for high-volume production chips • Good understanding of timing and P&R • Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution • Ability to write TCL scripts for STA and Fusion Compiler (FC) We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.