Jobs in Tel Aviv-Yafo

About Irregular Irregular is the first frontier security lab with the mission of protecting the world in the time of increasingly capable and sophisticated AI systems. We build next-generation defenses through high-fidelity research platforms that simulate and monitor real-world AI security scenarios. As AI systems become more powerful, we focus on staying ahead of emerging threats and vulnerabilities, ensuring these transformative technologies can be deployed safely and securely. About the role Our Operations team works across the business, supporting everything from commercial and marketing initiatives to finance, internal systems and employee experience. Reporting to the Head of Operations, you’ll take ownership of projects, build processes where they’re needed, and help teams get things done. This is a hands-on role for someone who enjoys variety, learns quickly and can turn an unfamiliar challenge into a clear plan and a completed project. What you’ll do • Lead projects across the company: Own operational initiatives from defining the need through execution, coordinating stakeholders, budgets and timelines. • Support business and commercial operations: Partner with business teams, Legal and Finance to coordinate customer onboarding, procurement requirements and other commercial processes. • Support marketing operations: Coordinate the execution of events, conferences, campaigns and launches, including agencies, vendors, materials, budgets and logistics. • Build processes and systems: Identify gaps, improve workflows and implement tools and automation that help teams work more effectively. • Manage vendors and purchasing: Own sourcing, negotiations, onboarding, renewals and ongoing service management across company needs. • Support financial operations: Manage purchasing and invoice workflows, track spending against budgets, and identify opportunities to improve efficiency and reduce costs. • Coordinate company infrastructure: Work with IT and security providers on equipment, access, service delivery and operational projects. • Support people and workplace operations: Partner with HR on onboarding, offboarding and employee initiatives, and help manage office needs as the company grows. • Take on emerging priorities: Research options, recommend solutions and independently drive new initiatives as business needs evolve. What you’ll bring • 4+ years of experience in operations, business operations or a similarly broad role, including hands-on experience at a startup - a must. • A track record of delivering projects involving multiple teams and managing several priorities simultaneously. • Experience building or improving processes, rather than only following established ones. • Strong organizational skills, attention to detail and reliable follow-through. • Good business judgment, confidence working independently and the ability to recognize when to escalate. • Comfort with budgets, spreadsheets and operational data. • Experience managing vendors and working with internal stakeholders and external partners. • Confidence in learning new systems and using AI and automation tools in your work. • Excellent Hebrew and English, written and spoken. • A practical, collaborative approach and equal willingness to lead a project or handle the details needed to complete it. An advantage: Experience supporting marketing or commercial operations, familiarity with CRM and project management tools, or experience in AI or cybersecurity.

About Irregular Irregular is the first frontier security lab with the mission of protecting the world in the time of increasingly capable and sophisticated AI systems. We build next-generation defenses through high-fidelity research platforms that simulate and monitor real-world AI security scenarios. As AI systems become more powerful, we focus on staying ahead of emerging threats and vulnerabilities, ensuring these transformative technologies can be deployed safely and securely. About the Role We’re looking for a Senior SecOps Engineer to own and evolve the security infrastructure, tooling, and controls that protect Irregular’s engineering environment. This is a hands-on security engineering role focused on building, implementing, and operating the systems that enable our engineering teams to work securely at scale. You’ll work closely with our Infrastructure Engineers and the broader Engineering team to embed security into our infrastructure and development environment without slowing teams down. You’ll take ownership of security tooling and posture management across our environment — from evaluating and deploying new security technologies to continuously improving how we identify, prioritize, and remediate security risks. We’re looking for someone with a strong background in Security Operations, Infrastructure Security, or Security Engineering who has operated and secured modern engineering environments. Representative Responsibilities • Own, operate, and continuously improve Irregular’s security infrastructure, tooling, and controls across cloud infrastructure, engineering systems, identity, and endpoints. • Evaluate, implement, and integrate security technologies across our engineering environment. • Own security posture and vulnerability management, including identifying, prioritizing, tracking, and driving remediation of security risks. • Partner closely with Infrastructure and Engineering teams to identify security gaps and implement practical, scalable solutions. • Integrate security tooling into engineering workflows, including vulnerability and dependency scanning tools • Build and improve security monitoring, detection, alerting, and incident response capabilities. • Automate security operations and controls to improve coverage, consistency, and efficiency. You may be a good fit if you have • Significant hands-on experience in Security Operations, Infrastructure Security, or Security Engineering. • Experience owning security infrastructure and tooling in a modern, cloud-based AWS environment. • Strong understanding of cloud and infrastructure security, identity and access management, endpoint security, vulnerability management, and security monitoring. • Hands-on experience evaluating, deploying, integrating, and operating security tools and security posture management platforms. • Experience implementing security controls in close collaboration with Infrastructure and Engineering teams. • The ability to independently identify security gaps, design solutions, and drive implementation end-to-end. • Strong ownership mentality and the ability to operate effectively in a fast-moving, high-ambiguity environment. Nice to Have • Hands-on experience with, • penetration testing, security research or offensive security. • cloud security posture management (CSPM) and related security platforms. • application Security and secure software development best practices. • building security automation or internal security tooling. • Experience translating offensive security knowledge into detection engineering, incident response, threat hunting, and security monitoring improvements. • Hands-on security training or certifications demonstrating strong practical offensive and defensive security skills, such as OSCP, OSCE, or equivalent.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly. As a Senior Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity. Key Responsibilities • Verification Environment Development • Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks • Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing • Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified • Coverage & Quality Assurance • Implement functional coverage models and analyze results to identify gaps in the verification process • Drive designs toward 100% verification closure through comprehensive test development • Contribute to verification methodology improvements and best practices • Debug & Cross-Functional Collaboration • Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle • Apply analytical skills and debugging techniques to solve intricate verification challenges • Collaborate effectively in a fast-paced, team-oriented R&D environment Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 3+ years of proven experience in ASIC verification within the semiconductor industry • Hands-on experience developing components within complex verification environments using SystemVerilog • Strong working knowledge of standard verification methodologies, specifically UVM • Sharp analytical mind with passion for debugging and technical problem-solving • Excellent communication skills with ability to thrive in collaborative R&D environments Preferred Qualifications • Master's degree in Electrical Engineering or related field • Familiarity with Formal Verification or Emulation flows • Basic proficiency in scripting languages such as Python or Tcl to automate verification tasks • Exposure to industry-standard protocols such as AMBA, PCIe, Ethernet, or CXL • Experience with assertion-based verification and constrained-random testing • Background in connectivity or networking silicon verification We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we are seeking a motivated Physical Design Student to join our founding local engineering team. This is a unique opportunity to kickstart your career in the semiconductor industry. Working alongside senior industry veterans, you will gain hands-on experience in backend execution and advanced methodologies for cutting-edge chips that power the world's largest AI clusters. If you are passionate about silicon hardware, eager to learn, and thrive on solving complex engineering challenges, this role offers the perfect bridge between your academic studies and a high-impact career. Key Responsibilities Guided Implementation & Learning • Partner with and learn from senior engineers to support the physical implementation journey, including synthesis, floorplanning, Place & Route (P&R), and Clock-Tree Synthesis (CTS) • Assist in macro-level implementation and develop hands-on skills in complex layout routing • Participate in deep-submicron process challenges under close professional mentorship Signoff & Design Integrity Support • Assist in running engineering checks for design integrity, including Static Timing Analysis (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR) • Learn to apply Logic Equivalence Checking (LEC) to help guarantee design correctness • Gain exposure to the rigorous flows required to ensure first-pass silicon success Scripting & Cross-Functional Collaboration • Leverage and develop scripting tools to automate repetitive tasks and optimize the engineering environment • Collaborate with Architecture, Design, and DFT teams to understand how different chip design disciplines intersect • Actively participate in team reviews and technical discussions to ramp up backend methodologies Basic Qualifications • Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field • Strong academic foundation in digital systems, VLSI design, or semiconductor devices. • Familiarity with Python, TCL, Bash, or Perl. • Ability to work at least 2 days per week at our Haifa/Tel Aviv Center • A "can-do" attitude with a passion for solving complex technical challenges • Fluent in Hebrew and English with the ability to work effectively in a team environment Preferred Qualifications • Prior experience from a previous VLSI/Hardware student position or a significant academic project in physical design/VLSI • Hands-on university lab experience with industry-standard EDA tools (e.g., Synopsys Fusion Compiler/ICC2, Cadence Innovus) • Understanding of basic verification concepts (STA, DRC, LVS) • Fast learner with a proactive attitude and a passion for deep-tech hardware infrastructure We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Manager Design Verification Tel Aviv District, Israel Astera Labs is seeking an experienced Manager, Design Verification to lead a team responsible for verifying the next generation of connectivity silicon powering the world's largest AI clusters. In this role, you will drive verification strategy and execution for complex SoC and IP designs supporting PCIe, CXL, Ethernet, UALink, and other advanced interconnect technologies. You will partner closely with Architecture, Design, Firmware, Post-Silicon Validation, and Program Management teams to ensure first-pass silicon success while scaling methodologies and processes across a growing organization. Key Responsibilities Verification Leadership • Lead and mentor a team of Design Verification engineers. • Define verification strategies, schedules, and execution plans for IP, subsystem, and SoC-level verification. • Drive verification planning, resource allocation, and project execution to meet aggressive tapeout schedules. Verification Development & Execution • Own verification sign-off criteria, coverage metrics, and quality standards. • Develop and review UVM/SystemVerilog testbenches, checkers, scoreboards, and verification components. • Collaborate with Design and Architecture teams to ensure comprehensive verification of specifications and microarchitectures. Methodology & Quality • Establish and improve verification methodologies, infrastructure, and best practices. • Establish reusable verification frameworks across multiple projects. • Ensure high-quality metrics-driven verification sign-off. Cross-Functional Collaboration • Work closely with RTL Design, DFT, Firmware, Post-Silicon Validation, and Physical Design teams. • Support bring-up and debug activities by correlating pre-silicon and post-silicon results. • Contribute to technical roadmap discussions and verification planning for future products. Basic Qualifications • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field. • 8+ years of ASIC/SoC verification experience. • 4+ years of technical leadership or people management experience. • Strong expertise in SystemVerilog and UVM. • Experience creating complex verification environments from architecture through sign-off. • Familiarity with SoC architectures and high-speed interfaces. Preferred Qualifications • Experience verifying PCIe Gen5/Gen6, CXL, Ethernet, UCIe, UALink, or similar protocols. • Knowledge of advanced SoC architectures and coherent fabrics. • Proven track record of shipping complex silicon products successfully. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. We are seeking an experienced Principal Architect to lead the architecture of high-performance connectivity solutions, with a strong focus on PCIe, high-speed networking, and Ethernet-based systems. This role will define next-generation architectures for AI infrastructure, working at the intersection of silicon, system, and protocol design. You will play a key role in shaping innovative solutions that enable hyperscale customers to build scalable, high-bandwidth, and low-latency systems. This is a unique opportunity to join a new and growing Israel site, influence technical direction, and take ownership of critical architectural decisions impacting industry-leading products. Key Responsibilities • Define and drive system and chip-level architecture for high-speed connectivity products • Lead architecture for PCIe-based interconnects, networking protocols, and Ethernet subsystems • Analyze system requirements and translate them into scalable and efficient hardware architectures • Drive tradeoff analysis across performance, power, latency, area, and cost • Collaborate with cross-functional teams including RTL, Physical Design, Firmware, Validation, and Product Engineering • Define and review micro-architecture specifications and ensure alignment across teams • Contribute to standard-based and custom protocols for next-generation AI infrastructure • Support performance modeling, simulation, and architectural validation • Work closely with customers and partners to understand emerging use cases and requirements • Mentor engineers and help build strong technical leadership within the Israel R&D center Basic Qualifications • 10+ years of experience in semiconductor architecture, ASIC design, or system engineering • Strong expertise in PCIe architecture (Gen4/5/6+) and its ecosystem • Deep understanding of Networking and Ethernet (e.g., 25G/50G/100G/400G and beyond) • Experience designing high-speed, low-latency data paths • Solid understanding of SoC architecture and integration challenges • Experience working across full chip development lifecycle • Strong analytical and problem-solving skills with ability to evaluate complex tradeoffs • Ability to influence and collaborate across multiple engineering domains Preferred Experience • Experience with CXL, NVLink, UALink, or other advanced interconnect protocols • Background in AI/ML infrastructure, data center systems, or hyperscaler environments • Experience with SerDes-based systems and high-speed PHY integration • Familiarity with networking stacks, switching, or RDMA technologies • Experience with performance modeling tools and architectural simulators • Knowledge of power/performance optimization techniques at system level • Track record of driving architecture from concept to silicon We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Principal DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters. As a Principal DFT Engineer, you will provide technical leadership across the full DFT lifecycle—from architecture and specification through implementation, verification, and silicon bring-up. You will define and drive DFT strategy, establish robust methodologies, and lead execution to ensure high test quality and manufacturability. This role requires deep expertise, cross-functional influence, and the ability to drive DFT excellence across projects and teams. This is a critical leadership position with high impact on first-pass silicon success and production quality for next-generation AI connectivity solutions. Key Responsibilities DFT Architecture & Technical Leadership • Define and own DFT architecture for complex SoCs, including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG strategies • Lead DFT planning, specification, and quality tracking across the project lifecycle • Provide technical leadership and drive DFT sign-off readiness to ensure successful tapeout Execution Across the Full Lifecycle • Lead DFT implementation, integration, and verification at block, full-chip and chiplet levels • Own end-to-end DFT activities from specification through silicon bring-up and production support • Ensure high test coverage, robust pattern generation, and alignment with manufacturing requirements Methodology & Cross-Functional Impact • Develop and drive scalable DFT methodologies, flows, and automation frameworks • Collaborate closely with RTL, Physical Design, STA, and Test Engineering teams to ensure design-for-test readiness • Optimize DFT integration across front-end and backend flows to improve quality, PPA, and turnaround time Basic Qualifications • Bachelor’s degree in Electrical Engineering or related technical field (Master’s preferred) • 12+ years of experience in DFT design, implementation, and verification for complex ASIC/SoC designs • Proven experience in leading DFT activities across full chip development cycles • Deep expertise in DFT techniques including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG • Strong understanding of DFT and Physical Design flows, including timing implications and integration challenges • Experience with industry-standard DFT tools (Siemens Tessent, Synopsys TestMAX or equivalent) • Solid experience with DFT verification methodologies and coverage analysis • Strong scripting skills (Tcl, Python, or Perl) for automation and flow development Preferred Qualifications • Experience with advanced process nodes (7nm and below) • Background in high-speed connectivity designs (PCIe, Ethernet, CXL, or similar) • Experience with hierarchical DFT methodologies and large multi-die or chiplet-based systems • Knowledge of silicon bring-up, production test flows, and yield optimization • Familiarity with STA, low-power design, and CDC as it relates to DFT integration • Strong leadership and communication skills, with ability to influence cross-functional teams globally We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters. As a DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools—you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity. Key Responsibilities • DFT Architecture & Strategy • Be part of the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support • Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards • Design and implement DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG for high-end devices • Test Pattern Development & Optimization • Generate and optimize high-quality test and debug patterns for production • Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance • Drive test coverage and quality metrics to meet stringent manufacturing requirements • Cross-Functional Collaboration & Methodology Innovation • Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR • Participate in developing and maintaining cutting-edge DFT implementation flows • Automate and improve methodologies using advanced scripting and tools Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 4+ years of hands-on experience in DFT roles at semiconductor companies • Experience in DFT flows and architectures including JTAG/iJTAG, MBIST, Scan, and ATPG • Good understanding of logic design, verification, debug, and Static Timing Analysis (STA) • Scripting proficiency in Tcl, Perl, Python, or Shell for automation and innovation Preferred Qualifications • Master's degree in Electrical Engineering or related field • Experience with industry-standard EDA tools from Synopsys (TestMAX) or Siemens (Tessent) • Experience in chip bring-up and mass production activities • Background in advanced process technologies (7nm and below) • Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) and their specific test requirements • Excellent communication skills with ability to work effectively in global team environments We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. The Role and Its Impact Our firmware team develops the embedded firmware that brings Astera Labs' compute connectivity silicon to life, from boot and initialization through link management, telemetry, error handling, and diagnostics. This firmware runs on the embedded processors inside our chips and ships in data centers powering AI infrastructure around the world. Beyond the firmware, the team also develops the COSMOS SDK, the software layer customers and internal teams use to configure, monitor, update, and debug our devices in their systems. We are looking for an experienced firmware engineer and PCIe expert who enjoys working close to the hardware, owns features end to end, and has a proven track record of developing and debugging firmware both pre-silicon and post-silicon. You know PCIe in depth, from link training and enumeration to error handling and recovery, and you're the person others turn to when a PCIe link or device misbehaves. You understand the whole system, not just the chip: how our devices behave inside customer platforms, and how a customer requirement turns into firmware and SDK. You'll work alongside architects, design and verification engineers, validation teams, and our global firmware teams to take new products from early pre-silicon development through bring-up and into customer deployment. What You'll Be Doing • Having fun! by being part of a very strong and cohesive group. • Design and develop real-time embedded firmware in C, including low-level drivers and control logic for complex hardware blocks • Own PCIe firmware features end to end: link training, enumeration, error handling, and recovery • Develop and debug firmware pre-silicon (emulation) and lead post-silicon bring-up and debug in the lab • Debug complex PCIe and system-level issues with architecture, design, validation, and customer teams • Develop and extend the company SDK in step with firmware features • Support customer requests and adjust firmware and SDK development to meet their needs What We're Looking For Required: • BSc/MSc in Computer Science, Electrical Engineering, Computer Engineering, or a related field • 10+ years of hands-on experience as a firmware engineer • Proven experience in embedded and real-time firmware development • Strong programming skills in C on resource-constrained, bare-metal, or RTOS-based systems • Solid understanding of processor architecture, memory-mapped registers, interrupts, and HW/SW interaction • Expert-level knowledge of PCIe: LTSSM and link training, enumeration, configuration space, error handling (AER), and reset and recovery flows • Experience with PCIe protocol analyzers and exercisers (e.g., Teledyne LeCroy, Keysight) • Proven hands-on experience in both pre-silicon and post-silicon firmware development and debugging, including silicon bring-up of new SoCs • Strong debugging skills on real hardware using JTAG debuggers, logs, and register-level analysis • Broad system-level understanding of how silicon, firmware, SDK, host software, and platform interact, with the ability to turn customer requirements into technical solutions • A team player with excellent communication skills who works well in a collaborative, cross-site environment • Comfort with ambiguity and ownership in a fast-moving, high-growth company Location This position is based in our Tel Aviv, Israel office. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Principal Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters. As an Principal Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity. Key Responsibilities • Emulation Flow Execution & Implementation • Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging • Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies • Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market • System-Level Debug & Validation • Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs • Ensure rapid cycles from RTL to functional stability through systematic debug approaches • Own technical blocks and drive them to completion independently • Cross-Functional Collaboration • Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios • Ensure seamless hardware-software integration for AI infrastructure connectivity • Collaborate with Design and Verification teams to optimize emulation strategies Basic Qualifications • Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field • 10+ years of hands-on experience in Emulation at semiconductor companies • Deep expertise in emulation flows for large-scale chips using industry-standard emulators (Zebu, Palladium, or Veloce) • Strong background in SystemVerilog for developing, testing, and debugging complex SoC designs • Experience developing and maintaining execution flows for building, running, and debugging emulation models • "Can-do" approach with ability to own technical blocks and drive them to completion independently Preferred Qualifications • Master's degree in Electrical Engineering, Computer Engineering, or related field • Familiarity with EDA tools for Lint, Clock Domain Crossing (CDC), simulation, and synthesis • Proficiency in scripting languages such as Python or TCL for automation and flow enhancement • Experience with standard debug environments (e.g., Verdi) • Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) • Background in hardware-software co-verification methodologies We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is a hyper-growth connectivity company building the purpose-built silicon that powers rack-scale AI infrastructure. As a Principal Physical Design Engineer and Team Lead in Israel, you will lead physical design teams that take complex, high-speed mixed-signal and digital SoCs from RTL handoff through tapeout. You will set the technical direction, drive execution across multiple projects, and grow the engineers around you, partnering closely with RTL, DFT, analog, and architecture teams. Your work will directly shape the performance, power, and area of products that connect the world's most demanding AI platforms. Key Responsibilities • Technical Leadership and Team Execution • Lead and mentor physical design engineers, setting priorities, assigning work, and ensuring high-quality, on-time delivery • Drive physical design projects end to end, including planning, scheduling, risk management, and status reporting • Define and evolve physical design methodologies, flows, and best practices across the team • Physical Implementation • Own block-level and top-level implementation: floorplanning, placement, clock tree synthesis, routing, and optimization • Drive timing closure, power integrity, and signal integrity to meet aggressive PPA targets in advanced process nodes • Lead physical verification and sign-off activities, including STA, IR/EM, DRC, LVS, and ECO management • Cross-Functional Collaboration • Partner with RTL design, DFT, analog, and architecture teams to resolve cross-domain implementation challenges early • Work with foundry, EDA vendors, and IP providers to ensure smooth tapeout and silicon bring-up • Contribute to hiring, onboarding, and professional development of team members Basic Qualifications • 10+ years of hands-on experience in physical design of complex SoCs or ASICs • Proven experience leading projects and technical teams through one or more full-chip tapeouts • Deep expertise with industry-standard physical design and sign-off tools (e.g., Cadence Innovus, Synopsys Fusion Compiler/ICC2, PrimeTime, Calibre) • Strong knowledge of timing closure, power/clock distribution, and physical verification in advanced process nodes • Excellent communication skills and the ability to work in a fully in-person, collaborative environment Preferred Qualifications • Experience with high-speed interface designs such as PCIe, Ethernet, or SerDes-based products • Proficiency in scripting languages such as Tcl, Python, or Perl for flow automation • Experience with hierarchical design, low-power methodologies, and ECO-driven closure • Demonstrated ability to mentor engineers and drive continuous improvement in team processes We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Staff / Principal ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects. As a Staff / Principal ASIC Design Engineer, you won't just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity. Key Responsibilities • Design Ownership & Implementation • Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support • Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions • Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams • Quality Assurance & Design Optimization • Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient • Apply design techniques to meet PPA (Power, Performance, Area) targets • Contribute to design quality through verification and validation activities • Methodology Innovation & Collaboration • Participate in design methodology improvements and tool automation initiatives • Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter • Collaborate effectively across teams to ensure seamless integration Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 5+ years of experience in logic design at semiconductor companies • Knowledge and experience in Verilog and/or SystemVerilog • Excellent communication skills with ability to work effectively across teams • Understanding of digital design principles and RTL coding best practices Preferred Qualifications • Master's degree in Electrical Engineering or related field • Knowledge of DDR and PCIe protocols and implementation • Understanding of power management techniques for low-power design • Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis • Proficiency in scripting languages such as Python or Perl • Experience with high-speed serial interface designs or connectivity protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up. If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us. As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the world’s largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale. Key Responsibilities • Execute SoC Top-level physical design and actively drive full-chip convergence • Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff • Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR) • Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon • Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration Basic Qualifications • B.Sc. or M.Sc. in Electrical Engineering • 5+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below) • Proven experience executing complex block or chip-level projects with a proactive, "can-do" approach and excellent communication skills • Deep hands-on expertise in RTL2GDS flows, including P&R, STA, Physical Verification (DRC/LVS), Formal Verification, low-power implementation (UPF/CPF), and EMIR • Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2 or Cadence Innovus) • Practical experience handling both complex macro/subsystem-level designs and Full-Chip integration Preferred Qualifications • Deep understanding of Power & Noise analysis (EM/IR) • Experience with DFT (Design for Test) integration into the physical design flow • Background in high-speed interfaces or data center protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects. As a Senior ASIC Design Engineer, you won't just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity. Key Responsibilities • Design Ownership & Implementation • Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support • Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions • Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams • Quality Assurance & Design Optimization • Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient • Apply design techniques to meet PPA (Power, Performance, Area) targets • Contribute to design quality through verification and validation activities • Methodology Innovation & Collaboration • Participate in design methodology improvements and tool automation initiatives • Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter • Collaborate effectively across teams to ensure seamless integration Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 3+ years of experience in logic design at semiconductor companies • Knowledge and experience in Verilog and/or SystemVerilog • Excellent communication skills with ability to work effectively across teams • Understanding of digital design principles and RTL coding best practices Preferred Qualifications • Master's degree in Electrical Engineering or related field • Knowledge of DDR and PCIe protocols and implementation • Understanding of power management techniques for low-power design • Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis • Proficiency in scripting languages such as Python or Perl • Experience with high-speed serial interface designs or connectivity protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the world’s most demanding AI and cloud environments. Key Responsibilities • Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip • Collaborate closely with Physical Design team to insure a full power integrity • Partner with Package Design engineers to perform Chip-Package co-analysis (CPM) • Understand root-cause analysis for voltage drop violations and EM risks Basic Qualifications • Bachelor's or Master's degree in Electrical Engineering or a related technical field • 7+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products • Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, or Cadence Voltus) • Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm) • Deep understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture • Deep understanding of EM and trade-offs between signal EM and power grid (PG) EM Preferred Experience • Familiarity with thermal analysis tools and their interaction with electrical performance • Experience working with sign-off criteria and margins for high-volume production chips • Good understanding of timing and P&R • Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution • Ability to write TCL scripts for STA and Fusion Compiler (FC) We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters. As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You won’t just execute tasks; you will define the Formal verification strategy for chips that drive the world’s largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications. Key Responsibilities • Own and develop formal verification environments from scratch through to sign-off • Apply formal verification methodologies and strategies to prove the correctness of intricate designs • Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements • Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs • Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently • Architect and develop generic, common formal functions and properties to be reused across multiple projects Basic Qualifications • Bachelor's degree in Electrical Engineering or a related technical field • 4+ years of hands-on experience in Formal Verification within semiconductor companies • Deep expertise in formal verification methodologies, tools, and flows • Strong understanding of RTL design and verification principles • Experience with industry-standard formal verification tools (Jasper, VC Formal, or similar) • Excellent communication skills, strong analytical thinking, and a proactive, "can-do" approach to problem-solving Preferred Qualifications • Track record of successfully taking complex blocks or subsystems through the entire formal verification lifecycle • Experience with SystemVerilog UVM-based design verification • Knowledge of networking standards (Ethernet, NVLink, UALink, PCIe) • Background in high-speed serial interface verification We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. The Role and Its Impact Our firmware team develops the embedded firmware that brings Astera Labs' compute connectivity silicon to life, from boot and initialization through link management, telemetry, error handling, and diagnostics. This firmware runs on the embedded processors inside our chips and ships in data centers powering AI infrastructure around the world. Beyond the firmware, the team also develops the COSMOS SDK, the software layer customers and internal teams use to configure, monitor, update, and debug our devices in their systems. We are looking for an experienced firmware engineer who enjoys working close to the hardware, owns features end to end, and is equally comfortable in a pre-silicon emulation environment and in the lab with real silicon. You understand the whole system, not just the chip: how our devices behave inside customer platforms, and how a customer requirement turns into firmware and SDK. You'll work alongside architects, design and verification engineers, validation teams, and our global firmware teams to take new products from early pre-silicon development through bring-up and into customer deployment. What You'll Be Doing • Having fun! by being part of a very strong and cohesive group. • Design, implement, and maintain real-time embedded firmware in C for high-performance connectivity • Develop low-level drivers, initialization flows, interrupt handling, and control logic for complex hardware blocks • Bring up and debug firmware in pre-silicon environments (emulation) ahead of tape-out, and on silicon after it arrives • Work closely with architecture, design, and verification teams to define HW/FW interfaces and to resolve issues across the hardware/software boundary • Triage and resolve firmware issues reported by validation, product applications, and customers • Take part in design reviews and code reviews, and help improve our firmware quality, tooling, and development practices • Develop and extend the company SDK, including APIs, device management, firmware update, telemetry, and diagnostics capabilities, and keep it aligned with firmware features • Support customer requests and engagements together with product applications and field teams, analyze system-level use cases, and adjust firmware and SDK development to meet customer needs • Collaborate with firmware teams across sites to deliver features on schedule What We're Looking For Required: • BSc/MSc in Computer Science, Electrical Engineering, Computer Engineering, or a related field • 10+ years of hands-on experience as a firmware engineer • Proven experience in embedded and real-time firmware development • Strong programming skills in C on resource-constrained, bare-metal, or RTOS-based systems • Solid understanding of processor architecture, memory-mapped registers, interrupts, and HW/SW interaction • Strong debugging skills on real hardware using JTAG debuggers, logs, and register-level analysis • Broad system-level understanding of how silicon, firmware, SDK, host software, and platform interact, with the ability to turn customer requirements into technical solutions • A team player with excellent communication skills who works well in a collaborative, cross-site environment • Comfort with ambiguity and ownership in a fast-moving, high-growth company Advantage: • Experience with pre-silicon emulation platforms such as Cadence Palladium or Synopsys ZeBu • Knowledge of PCIe (link training, enumeration, configuration space, error handling) • Experience developing SDKs, host-side libraries, or APIs (C/C++ or Python) that interface with embedded firmware • Experience working directly with customers or supporting customer integration and field issues • Experience with silicon bring-up of new SoCs • Python scripting for test automation, debug, or data analysis We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Senior System Validation Engineer Astera Labs is seeking a motivated Senior System Validation Engineer to join our growing post-silicon validation team in Israel and support next-generation connectivity products for AI and data-center applications. In this role, you will perform system-level post-silicon validation, characterization, and debug across silicon, hardware, firmware, and software. You will support silicon bring-up and PVT/corner testing, develop and execute functional and system validation tests, analyze results, and work with cross-functional teams to identify and resolve complex system issues. This is a highly hands-on lab position. The primary location is Haifa, with temporary support at the Ramat Gan lab as needed. Key Responsibilities: • Develop and execute post-silicon functional and system validation from silicon bring-up through production readiness. • Run PVT, silicon corner, stress, characterization, and qualification testing across a wide range of operating conditions. • Develop validation tests to verify functionality, performance, stability, power, and operating margins. • Debug issues across silicon, hardware, firmware, drivers, and system software. • Validate high-speed interfaces such as PCIe, CXL, Ethernet/SerDes, and DDR, as well as common system interfaces. • Develop Python scripts and automation to improve validation coverage, regression, and test efficiency. • Analyze validation data, identify issues and trends, and drive problems to root cause and closure. • Work closely with hardware, architecture, firmware, software, design, and DV teams to investigate and resolve issues. • Support the transition of new silicon from initial bring-up to a qualified, production-ready product. • Operate system platforms and laboratory equipment to support validation and debug. • Document test results, issues, root cause, and recommendations and communicate findings clearly. Basic Qualifications: • B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, Computer Science, or a related field. • 6+ years of experience in post-silicon, system, hardware, or product validation. • Hands-on experience with SoC/silicon bring-up, functional validation, and system-level debug. • Experience developing and executing validation plans, test cases, and characterization experiments. • Strong Python scripting and test automation skills. • Strong hardware debugging, analytical, and problem-solving skills with the ability to work independently. • Experience debugging issues across hardware, firmware, and software. • Experience validating high-speed interfaces such as PCIe, Ethernet, SerDes, CXL, or DDR. • Hands-on experience working in a hardware or system validation laboratory. • Strong communication and cross-functional collaboration skills. Preferred Qualifications: • Experience with PVT validation, silicon corner testing, characterization, qualification, and margin analysis. • Experience with server, storage, networking, or AI infrastructure products. • Familiarity with PCIe/CXL architecture and high-speed SerDes technologies. • Experience with oscilloscopes, BERTs, protocol analyzers, traffic generators, or similar lab equipment. • Working knowledge of Python, firmware, Linux, and system-level software debugging. • Experience developing automated validation and regression environments. • Familiarity with Git and software development practices. • Experience with pre-silicon validation, emulation, or hardware prototyping. • Experience with system performance, throughput, latency, power, and stability testing. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. We are looking for a Post-Silicon Validation Engineer with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams. Key Responsibilities • Perform hands-on post-silicon validation • Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability. • Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements. • Drive complex issues from initial failure through root-cause analysis and final resolution. • Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries. • Validate PCIe functionality across different generations, platforms, configurations, and operating conditions. • Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests. • Develop automation to improve validation coverage, debug efficiency, and regression testing. Required Qualifications • BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience. • 5+ years of engineering experience in silicon validation, post-silicon debug, or high-speed interface development. • Strong hands-on knowledge of PCIe architecture and protocol. • Experience working with PCIe analyzers, state traces, registers, logs, eye diagrams, and/or signal-integrity measurements. • Strong problem-solving skills and ability to independently drive issues to root cause. • Experience working across hardware, firmware, and software boundaries. • Good scripting/programming skills, preferably Python • Good Linux knowledge and experience with Linux PCIe debug tools. • Strong communication and collaboration skills. Preferred Qualifications • Experience with PCIe Gen4/Gen5/Gen6/Gen7 • Hands-on experience with PCIe PHY, SerDes, equalization, lane margining, or signal integrity. • Experience with PCIe compliance and interoperability testing. • Experience debugging intermittent, marginal, thermal-sensitive, or corner-case PCIe failures. • Experience with PCIe switches, or networking/accelerator platforms. • Practical experience using AI/ML tools for engineering debug and automation. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity. Key Responsibilities • Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments • Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence • Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments • Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners • Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient Basic Qualifications • B.Sc. in Electrical Engineering or Computer Engineering • 6+ years of hands-on experience in Static Timing Analysis (STA) at semiconductor companies, specifically working on advanced process technologies. (Note: Adjust years of experience based on the exact level you are targeting) • Deep expertise in multi-scenario STA, as well as timing and SDC constraint development and verification at the block and subsystem levels • Solid understanding of advanced margining methodologies, including OCV, AOCV, and POCV, from synthesis through to final sign-off • Solid knowledge of physical design flows (Synthesis, P&R, Physical Verification) and how they intersect with timing closure Preferred Experience • Experience developing and validating constraints using industry-standard tools like Timing Constraints Manager (Synopsys) or TimeVision (Ausdia) • Proven track record of executing STA on complex Macro-level designs and supporting Full-Chip timing integration • Strong background in scripting (Tcl, Python, Perl) and automation to enhance timing closure efficiency We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.