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NVIDIA has been transforming computer graphics, PC gaming, accelerated computing, and AI for more than 25 years. Today, we are defining the next era of computing, where AI datacenters, GPUs, networking, and accelerated infrastructure work together as one system. We are looking for an outstanding engineer to join our software architecture group and help shape the next generation of NVIDIA networking products, SmartNICs, and DPUs. In this role, you will work closely with system architects, software/firmware engineers, hardware designers and product stakeholders to define component-level and system-level solutions for advanced datacenter platforms. You will join a team working at the intersection of AI networking, virtualization, operating systems, security, management, and programmable acceleration. Our mission is to push the boundaries of modern datacenter infrastructure and help define the platforms of tomorrow. What You’ll Be Doing: • Work with architects and engineers to define software architecture for NVIDIA networking devices, SmartNICs, and DPUs. • Analyze system requirements across networking protocols, virtualization, operating systems, security, management, and services. • Research new ideas, evaluate design alternatives, and build proof-of-concept models, simulations, and prototypes. • Collaborate with software, firmware, and hardware teams on HW/SW co-design, performance, scale, and resource-utilization challenges. • Learn complex datacenter technologies and turn them into clear architecture proposals, design documents, and technical presentations. What We Need To See: • Engineer holding a B.Sc. or M.Sc. in Computer Science, Electrical Engineering, Computer Engineering, or a related field. • 1+ years of relevant experience • Proven strong programming skills, in C/C++, preferably for large and complex embedded systems. • Solid understanding of operating systems, multi-threading, computer architecture, and software fundamentals. • Curiosity and ability to learn new technologies quickly, investigate deeply, and work through ambiguous problems. • Independent problem solver who also works well in a team environment. • Clear written and verbal communication skills. Ways To Stand Out From The Crowd: • Knowledge of networking protocols such as Ethernet, InfiniBand, RDMA, RoCE, TCP/IP, or congestion control. • Experience with Linux, Linux kernel, device drivers, embedded systems, or system software. • Experience building simulations, performance models, prototypes, or proof-of-concept software. • Exposure to virtualization, security, programmable acceleration, SmartNICs, DPUs, or DOCA. • Open-source contribution, previous internship experience, or hands-on project work in relevant technical domains. NVIDIA is widely considered one of the technology world’s most desirable employers. We are made up of forward-thinking, hardworking people who are passionate about solving some of the world’s most important computing challenges. NVIDIA is committed to fostering a diverse and inclusive work environment and is proud to be an equal opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The NVIDIA System-On-Chip (SOC) group is looking for a strong RTL Design Engineer to own the SOC clocking logic for our next-generation networking chips. Clocks are the backbone of the SOC. In this role you will own the clock generation, distribution, and control logic for the entire chip — PLL and reference clock integration, clock muxing and dividers, glitchless switching, clock gating, reset synchronization, and the clock domain crossing infrastructure that every unit on the die depends on. This is an RTL design role, not a circuit or transistor-level design role. You will translate micro-architecture specifications into high-quality synthesizable RTL, and drive that RTL through to silicon in close partnership with the micro-architecture, Design Verification, and Physical Design (backend) teams. You will also interact with CAD, Package Design, Software, and DFT teams. What you'll be doing: • Owning the SOC clocking logic end to end: writing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization, from micro-architecture specification through tape-out • Defining and implementing the SOC clock and reset architecture together with the micro-architecture team — collecting clocking requirements from every unit on the chip and turning them into a coherent, verifiable design • Owning clock domain crossing infrastructure and CDC closure across the SOC • Partnering with the micro-architecture team to review specifications, close on design intent, and provide feedback on implementation cost, timing, area, and power • Working hand-in-hand with the Physical Design (backend) team on clock tree implementation and constraints, partitioning, floorplan and timing feedback, trial synthesis, congestion and timing convergence, and physical design readiness • Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows • Driving design quality: lint, CDC/RDC, formal checks, synthesis QoR, connectivity and structural checks • Supporting SOC-level chip build and assembly, and developing/deploying automation flows that make RTL integration and design quality checking repeatable and scalable • Supporting emulation, firmware, and post-silicon bring-up customers of your design What we need to see: • B.Sc./M.Sc. in Electrical Engineering or Computer Engineering • 3+ years of relevant experience in RTL/logic design • Solid hands-on RTL design skills in Verilog/SystemVerilog, with a good understanding of synthesis, timing, and how RTL choices affect the physical implementation • Experience taking a design from micro-architecture specification through verification and physical implementation • Solid understanding of clocking and reset concepts: clock gating, clock muxing and dividers, glitchless clock switching, reset synchronization, and clock domain crossing • Familiarity with design quality tooling (lint, CDC/RDC, formal, synthesis) • Great teammate with strong communication skills across micro-architecture, DV, and backend teams Ways to stand out from the crowd: • Passion for quality, and a track record of clean deliveries to physical design, DV, emulation, firmware, and other downstream customers • Prior ownership of SOC-level clocking or reset architecture on a taped-out chip • Experience with PLL/clock generator integration and clock tree constraint development with backend teams At NVIDIA, you will be immersed in a diverse and encouraging environment where everyone is encouraged to do their best work. Join us and see how you can make a lasting impact on the world. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law

We are now looking for a Power Optimization and Analysis Engineer! NVIDIA prides ourselves on having energy-efficient products. We believe that continuing to maintain our products' energy-efficiency compared to competition is key to our continued success. As part of the u/arch team in the Switch group, you will be responsible for analyzing full chip and unit-level power data and driving the FE/BE ASIC teams to improve their units’ power efficiency; you will be responsible for researching, developing, and deploying methodologies to help NVIDIA's products become more energy efficient. Key responsibilities include developing techniques to model, analyze, and reduce power consumption of NVIDIA Switches product line. As a member of Switch u/arch Team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement power analysis and reduction techniques for NVIDIA's next generation switches. Your contributions will help us gain early insight into energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements. What You'll Be Doing: • Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency. • Develop and share best practices for performing pre-silicon power analysis. • Perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny. • Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes. • Select and run a wide variety of workloads for power analysis. • Prototype new architectural features in Verilog and power analysis. What We Need To See: • BSC or MS in Computer Engineering or Electrical Engineering • 5+ years of experience in chip design • Good and interpersonal skills; much collaboration with design teams is expected. • Familiarity with Verilog and ASIC design or verification. • Desire to bring data-driven decision-making and analytics to improve our products. • Strong coding/automation skills, preferably in Python, Perl, and C++. Ways to Stand Out From the Crowd: • Experience with Power Artist, PTPX (Prime Power RTL, RTL Architect). • Strong understanding of concepts of energy consumption, estimation, data movement and low power design.

NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance. • Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems. • Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification. • Taking part in flows development. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience. • 5+ years of experience in Physical Design. • Proven experience in RTL2GDS flows and methodologies. • Knowledge in physical design flows and methodologies (PNR, STA, physical verification). • Deep understanding of all aspects of Physical construction and Integration. • Strong background of Physical Design Verification methodology LVS/DRC. • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc). • Great teammate. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

We are looking for a highly motivated Senior Network Architect specializing in Advanced Packaging, to join our expert team and contribute to the advancement of high-performance computing. Our future InfiniBand, NVL, and Ethernet switches will be central to connecting and powering the world’s most advanced compute clusters. These include supercomputers dedicated to AI research and high-performance clusters in various sectors. As an Architect of Advanced Packaging at NVIDIA, you will engage with innovative technology. You will help create next-generation large radix switches. The products you develop will support many pioneering compute clusters and supercomputers. What you'll be doing: • Collaborate with cross-functional teams, including other architecture teams, logic build, system and hardware teams, to ensure the successful execution of the project optimizing our solution. • Crafting and architecting advanced packaging solutions for NVIDIA Systems. • Analyzing and determining the best approaches for our switch system solutions. • Successfully implementing and managing projects to meet ambitious performance targets. What we need to see: • BSc or MSc in Electrical Engineering / Computer Science or equivalent experience. • A proven track record with a minimum of 8 years of experience in Advanced Packaging. • Deep understanding of how to build and integrate systems with various technology components. • Proficiency in advanced system-level high-speed connectivity. • Excellent communication skills to effectively work with diverse teams and collaborators. • Can-do attitude and high energy with leadership and excellent interpersonal skills and possess the ability to learn sophisticated concepts in a fast-paced environment. • Possess strong managerial, problem-solving, and critical thinking skills. • Attention to details on building and high focus on build quality. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical build team in the industry!

NVIDIA Networking product security team is looking for an outstanding technical security architect with hands-on experience to help us improve the security posture of NVIDIA networking products. In this role you will partner with firmware, hardware, and architecture teams on the security architecture, to reduce risk, threats, and vulnerabilities while driving new security features that affect millions of devices all over the world! What you'll be doing: • Be involved in the security architecture of NVIDIA Networking firmware — trust boundaries, privilege separation between firmware domains, device identity and key storage, secure boot and chain of trust, and secure update and anti-rollback flows. • Perform security threat modeling of firmware and embedded subsystems across NVIDIA Networking products. • Analyze complex firmware and hardware/firmware interactions to identify security weaknesses, including boot flows, privileged execution environments, and host- and network-facing management interfaces. • Define security features and mitigations spanning the full device lifecycle — provisioning, attestation, debug authorization, runtime hardening, and field update. Guide the engineering teams throughout the implementation. • Translate threat models into actionable security requirements and architectural decisions, and review designs and implementations against them. • Partner with hardware and ASIC architects to specify the security primitives firmware depends on, and define how they are used across the product line. • Drive secure development practices for firmware — memory-safe coding patterns in C, static analysis, and fuzzing of firmware-exposed interfaces — and make sure development processes meet security and coding standards. What we need to see: • Academic degree in computer science, electrical engineering, or related field. Candidates with equivalent work experience will also be considered. • Demonstrated experience of 5+ years in product security, firmware security, or security research, including hands-on work with embedded or firmware codebases. • Experience defining security policy models — authorization schemes, RBAC, and administrative role separation — including how policy is expressed, enforced, and administered in production. • Familiarity with applied cryptography (including secure boot, code signing, and attestation), threat modeling, common attack vectors, and mitigation techniques. • Ability to work independently, and collaboratively in a constantly evolving environment. • Excellent communication and interpersonal skills. Ways to stand out from the crowd: • M.Sc. or PhD in computer science, electrical engineering, or related technical field. • Experience with hardware/software interfaces in networking devices — register and MMIO programming models, DMA, mailbox and doorbell mechanisms, PCIe configuration and management interfaces, and the firmware that drives them. • Experience with hardware roots of trust and hardware-enforced isolation (MPU/MMU, secure enclaves, fuse/OTP-based provisioning) in SoCs or ASICs. • Hands-on experience with networking software — device drivers, control plane, management interfaces, or embedded network operating systems — and an understanding of how these components interact with firmware. • Familiarity with high-scale deployment, the data center security ecosystem and its operational challenges. With highly competitive salaries and a comprehensive benefits package, NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people on the planet working for us and, due to unprecedented growth, our special engineering teams are growing fast. If you're a creative and autonomous engineer with a genuine passion for technology, we want to hear from you. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

NVIDIA Switches ASIC group is seeking a top-tier ASIC Power technical manager to lead the development of our next-generation ASICs Power execution, modelling, and optimization. Join us in shaping the future of technology! As an ASIC Power Project Lead, you will manage the pre-silicon Power activities of NVIDIA's most advanced and complex switch ASICs. You will collaborate with a cross-disciplinary team, interacting with unit-level ASIC, Physical Design, CAD, Package Design, Firmware & Software, DFT, System Design, Analog Design, and other specialized teams. What you’ll be doing: • Lead the ASIC Power execution from architecture stages until tape-out. • Post-Silicon Power Activities: Monitor and support chip Power from power-on and bring-up, quality phases, to mass production. • Power Execution Plans: Define and implement Power execution plans in collaboration with cross-discipline leaders. What we need to see: • BS or MS in Computer or Electrical Engineering or equivalent experience. • 15+ overall years of proven experience in chip design. • 8+ years of experience in VLSI / chip design, leading teams of at least 8 direct reports. • High system view with ability to collaborate with multiple interfaces. • Strong analytical and problem-solving skills. • Excellent communication and teamwork abilities. • Experience in ASIC power optimization, ASIC power modelling, thermal, reliability, Power Integrity, Package and Board design is a plus. If you are creative, autonomous, and love a challenge, we want to hear from you! Join NVIDIA and be a part of the team that is driving the future of technology.

We are seeking for an expert in SOC Design Integration Engineer with strong design fundamentals, to work in Switch Silicon group. You'll join a group of hardworking engineers to craft and implement the next generation innovative Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing best high-speed communication devices, delivering the highest throughput and lowest latency! What you'll be doing: • Work in a design integration team which responsible for all the switch design integration • Work closely with multiple teams within organizations such as Architecture, u-arch, designers, BackEnd and FW • Work on FullChip Assembly and drive cross-functional teams towards FullChip milestone execution • Be responsible for all the switch chip design architecture focusing on timing, area and power What we need to see: • Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience. • 5+ years of experience in RTL design integration • Experience in synthesis, physical design and DFT is a plus. • Background in RTL Build and Design Automation is a plus. • A team player with good communication and interpersonal skills. NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear from you. Come, join our Switch Silicon design team and help us build the next chip in this exciting and quickly growing field.

Our technology has no boundaries! NVIDIA is building the world’s most groundbreaking and state of the art accelerated compute platforms for the world to use. It’s because of our work that scientists, researchers and engineers can advance their ideas. We pioneered a supercharged form of computing loved by the fastest paced computer users in the world - scientists, designers, artists, and gamers. We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today, such as car and Pharmaceutical. As a high-performance system architect at NVIDIA, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world. What you’ll be doing: • Define the NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments). • Research of various solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW. • Developing models for simulations and performance testing, analysing the results and development of future HW and SW. • Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project. What we need to see: • B.Sc, M.Sc, or Ph. D degree in Computer Science, Computer Engineer, or Electrical Engineer. • At least 5 years of industry or research experience in computer networks. • Excellent understanding of large-scale networks behaviour and the effect of distributed computing workloads effect on the network. • Experience in development of simulation environments. • Possess strong managerial, problem solving and critical thinking skills. • Ability to work and operate in a highly dynamic environment. • Partner with multiple groups in the organization. Ways to stand out of the crowd: • Strong understanding in network protocols - such as InfiniBand, IP, TCP and RoCE and network topologies. • Good knowledge in Python, C++. • Good knowledge with AI models. • Familiarity with HPC environments, routing algorithms, Omnet++ and NS3 simulation environments. NVIDIA has some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you. We are committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. The GPU Networking Software Architecture team is looking for a Senior Software Architect to help shape software for next-generation AI infrastructure. In this role, you will combine hands-on software architecture and development with system-level thinking. You will collaborate with experienced architects and engineering teams across NVIDIA while expanding your software architecture skills. Join us to help build the technologies that connect and manage large-scale accelerated computing systems. What you’ll be doing: • Contribute to the architecture and prototyping of GPU networking software for large-scale AI infrastructure. • Analyze requirements, evaluate design alternatives, and document technical decisions and trade-offs. • Develop proofs of concept to evaluate interfaces, performance, resiliency, and software-hardware interactions. • Collaborate with GPU, switch, firmware, driver, networking software, product, and architecture teams to move concepts toward implementation. • Build knowledge of the GPU networking software stack and take increasing ownership of well-defined architectural areas. What we need to see: • B.Sc. or M.Sc. in Computer Science, Electrical Engineering, Computer Engineering, or a related field, or equivalent experience. • 5+ years of relevant software development experience in Linux environments. • Strong understanding of software engineering fundamentals, including debugging, testing, data structures, concurrency, and operating-system concepts. • Solid foundational knowledge of computer networking. • Ability to understand complex systems, reason about component interfaces and design trade-offs, and communicate technical ideas clearly. • Curiosity, initiative, collaborative problem-solving skills, and an eagerness to learn from experienced architects and engineers. • Ability to work effectively with teams across locations and time zones. Ways to stand out from the crowd: • Knowledge in one or more of the following: Ethernet and IP datacenter protocols, management and telemetry protocols, GPU interconnects, Linux kernel or driver development, and network operating systems. • Experience building prototypes or contributing to system-level architecture and design documents. • Familiarity with AI communication libraries or programming models such as NCCL, UCX, MPI, CUDA, or equivalents. • Knowledge of Kubernetes, containers, or cloud-native infrastructure. • Experience analyzing performance, reliability, resiliency, or observability in complex software systems. NVIDIA is widely considered one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you are creative, collaborative, and excited to grow from hands-on software development into software architecture, we want to hear from you.

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The NVIDIA System-On-Chip (SOC) group is looking for a Senior RTL Design Engineer to serve as the technical lead for clocks development on our next-generation networking chips. Clocks are the backbone of the SOC. In this role you will lead the development of the chip's clocking logic — PLL and reference clock integration, clock generation, distribution, muxing and dividers, glitchless switching, clock gating, reset synchronization, and the clock domain crossing infrastructure that every unit on the die depends on. This is an RTL design and technical leadership role, not a circuit or transistor-level design role. Working from the clock architecture defined with the architecture and micro-architecture teams, you will lead its implementation in RTL, guide other engineers contributing to it, and drive it through to silicon in close partnership with Design Verification and Physical Design (backend). You will also interact regularly with CAD, Package Design, Software, and DFT teams. What you'll be doing: • Acting as the technical lead for SOC clocks development — leading the implementation of the clocking logic from specification through tape-out and bring-up • Working with the architecture and micro-architecture teams on the SOC clock and reset scheme: collecting clocking requirements from units across the chip, feeding back implementation and timing considerations, and translating the agreed scheme into a verifiable design • Writing and reviewing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization • Leading and mentoring other RTL engineers working on clocking: reviewing designs, setting coding and quality standards, and distributing work across the team • Working hand-in-hand with the Physical Design (backend) team on clock tree implementation, SDC/timing constraints, partitioning, floorplan feedback, trial synthesis, and timing convergence • Partnering with Design Verification on clocking testplans, functional and gate-level debug, and coverage closure • Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows • Representing clocking implementation in cross-functional design reviews with architecture, PD, DV, DFT, and CAD stakeholders What we need to see: • B.Sc./M.Sc. in Electrical Engineering or Computer Engineering • 8+ years of relevant experience in RTL/logic design, with multiple chips taken to tape-out • Demonstrated technical leadership: leading a design area through implementation and tape-out, mentoring engineers, and coordinating across teams • Expert hands-on RTL design skills in Verilog/SystemVerilog, with strong understanding of how RTL choices affect synthesis results, timing, area, and power • Deep understanding of clocking and reset design: clock gating, clock muxing and dividers, glitchless clock switching, reset synchronization, and clock domain crossing • Proficiency with design quality tooling — lint, CDC/RDC, formal verification, synthesis, and static timing analysis (STA) — including the ability to interpret results and drive fixes back into the RTL • Experience taking a design from architecture and micro-architecture specification through verification, physical implementation, and silicon bring-up • Great teammate with strong communication skills across micro-architecture, DV, backend, DFT, and software teams Ways to stand out from the crowd: • Prior hands-on experience with SOC-level clocking or reset logic on a taped-out chip • Experience with PLL/clock generator integration and clock tree constraint development with backend teams • Experience with high-speed networking, interconnect, or fabric designs • Background with low-power design techniques (clock gating, DVFS, power domains, UPF) • Experience building automation for RTL integration, chip assembly, or design quality flows At NVIDIA, you will be immersed in a diverse and encouraging environment where everyone is encouraged to do their best work. Join us and see how you can make a lasting impact on the world. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

NVIDIA Switches ASIC group is seeking a top-tier ASIC technical manager to lead the development of our next-generation ASICs. Join us in shaping the future of technology! As an ASIC Project Lead, you will manage the pre-silicon development activities of NVIDIA's most advanced and complex switch ASICs. From concept to tape-out and from chip power-on to mass production, you will be the driving force behind the entire lifecycle of our ASIC projects. You will collaborate with a cross-disciplinary team, interacting with unit-level ASIC, Physical Design, CAD, Package Design, Firmware & Software, DFT, System Design, Analog Design, and other specialized teams. What you’ll be doing: • Lead the ASIC development from concept and architecture stages through micro-architecture, design, verification, and physical design until tape-out. • Post-Silicon Activities; Oversee chip power-on, bring-up, quality phases, and mass production. • Execution Plans; Define and implement execution plans in collaboration with cross-discipline leaders in unit level, full-chip, physical design, and firmware/software emulation. • Roadmap Definition; Contribute to the definition of NVIDIA's switch ASIC roadmap. What we need to see: • BS or MS in Computer or Electrical Engineering or equivalent experience. • 15+ overall years of proven experience in chip design. • 8+ years of experience in chip design/verification management, leading teams of at least 8 direct reports. • Proficiency in RTL design (Verilog), verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation. • High system view with ability to collaborate with multiple interfaces. • Strong analytical and problem-solving skills. • Excellent communication and teamwork abilities. • Experience in synthesis, and physical design is a plus. If you are creative, autonomous, and love a challenge, we want to hear from you! Join NVIDIA and be a part of the team that is driving the future of technology. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance. • Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems. • Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification. • Taking part inflows development. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent experience. • 5+ years of relevant experience. • Proven experience in RTL2GDS flows and methodologies. • Knowledge in physical design flows and methodologies (PNR, STA, physical verification). • Deep understanding of all aspects of Physical construction and Integration. • Knowledge in Physical Design Verification methodology LVS/DRC. • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). • Great teammate. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

NVIDIA is looking for best-in-class Physical Design Power Engineer to join our outstanding Networking Silicon Power engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput, lowest latency and best Power! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you will be doing: • Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints. • Optimization involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes. • Power estimation and power modeling. What we need to see: • B.SC./ M.SC. or equivalent experience in Electrical Engineering/Computer Engineering. • 1+ years of experience in physical design and/or BE power optimization aspects. • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). • Native ability to leverage modern AI tools to accelerate engineering workflows, productivity, and problem-solving. • Knowledge in physical design flows and methodologies (PNR, STA, physical verification) is an advantage. • FE design experience is an advantage. • Excellent problem-solving, partnership, and interpersonal skills. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

We are hiring a skilled DPU Performance Validation Engineer for our DPU product lines. This includes chip architecture performance characterization, debug, and validation across single-die and multi-die systems. Working in the Network Silicon Engineering group, you will be responsible for debugging, analyzing, and validating performance and functional behavior of current and future NVIDIA silicon devices. You will collaborate with Chip Design, Verification, FW, and Architecture teams to ensure successful product development with bold product cycles. The qualified candidate should be comfortable working in Simulation and Emulation environments, with strong skills in RTL-level debug, waveform analysis, and system-level performance root cause analysis. What you will be doing: • Learn and analyze system-level operation of NVIDIA DPUs • Debug and root-cause performance issues in pre-silicon environments, across RTL, waveform traces, and multi-die system simulations. • Collaborate closely with design, verification, architecture, and performance modeling teams to isolate and fix issues. • Develop and improve validation methodologies for performance experiments and data collection. • Automate repetitive debug and validation tasks to scale coverage and efficiency. What we need to see: • B.Sc. in Electrical Engineering, Computer Engineering, or equivalent • 3+ years of experience in ASIC development/validation. • Strong background in ASIC debug, including reading RTL, analyzing waveforms, and root-causing functional or performance issues. • Hands-on experience with performance validation and analysis at the system level (die-level or multi-die systems). • Proficiency with Python and C/C++ in a Linux environment. • Excellent interpersonal skills and ability to work optimally as part of a multi-functional team. Ways to stand out from the crowd: • Shown expertise in performance modeling, traffic generation, or architecture studies. • Experience with modern interconnects and protocols (e.g., PCIe, Ethernet, CHI). • Familiarity with emulation platforms (e.g., Palladium, Veloce, FPGA prototyping). • Passion for experimental work, data-driven validation, and creative problem solving. NVIDIA is widely considered to be one of the technology world’s most desirable employers with some of the most forward-thinking, inventive, and hardworking people working here – we need your help to build our future. Are you creative, high-reaching, and love challenges? We want to hear from you!

NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance. • Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems. • Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification. • Taking part inflows development. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent experience. • 1+ years of relevant experience. • Proven experience in RTL2GDS flows and methodologies. • Knowledge in physical design flows and methodologies (PNR, STA, physical verification). • Deep understanding of all aspects of Physical construction and Integration. • Knowledge in Physical Design Verification methodology LVS/DRC. • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). • Great teammate. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

NVIDIA is the engine of modern AI and accelerated computing, and power efficiency sits at the heart of everything we build. We are looking for a Senior ASIC Design Engineer to join our Chip Design team and take ownership of Power Management IP — from micro-architecture definition all the way through to post-silicon enablement. You will be a key player in developing and enabling new technologies that scale across NVIDIA's product lines. If you are passionate about front-end micro-architecture and design and want to see your blocks come to life in silicon, we want to hear from you! What you'll be doing: • Owning the front-end micro-architecture and design of Power Management IP ASIC blocks, from the IP definition phase through the full design cycle and into post-silicon bring-up and enablement. • Serving as a key player in the development and enablement of new power management technologies across NVIDIA's product lines. • Delivering high-quality, synthesizable RTL as part of the IP Chip Design team. • Partnering closely with architecture, verification, physical design, and validation teams to drive successful tape-out and silicon bring-up. • Leading post-silicon debug, characterization, and enablement activities to bring your blocks from concept to working silicon. What we need to see: • BSc or MSc in Electrical Engineering, Computer Engineering, or a related field (or equivalent experience). • 12+ years of hands-on RTL design experience. • Proven experience bringing a block from the development phase all the way through to post-silicon bring-up and enablement. • Strong background in front-end ASIC micro-architecture and design. • Solid command of the full IP/ASIC design flow, from definition through post-silicon. • A collaborative mindset and the drive to be a key contributor within a world-class design team. Ways to stand out from the crowd: • Hands-on experience with Power Management IP. • A track record of contributing to new technology development and enablement. • Deep post-silicon validation and debug expertise. • Familiarity with low-power design techniques and methodologies. NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you! NVIDIA is committed to fostering a diverse work environment and is proud to be an equal opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, disability, or any other characteristic protected by law.

As a chip design Engineer at NVIDIA Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! What you'll be doing: • Work in a combined design and verification team which develops some of the switch silicon core units • Build reference models, verify and simulate chip blocks/entities according to specifications under challenging constraints with high orientation to power, area, and performance. • Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW. What we need to see: • B.Sc. in Electrical/Computer Engineering or equivalent experience. • 5+ years of experience in Verification or RTL design. • Knowledge in network protocols and/or HPC. • A team player with good communication and interpersonal skills.

We are now looking for a best-in-class Chip Design Verification Engineer to join our outstanding GPU-Networking Silicon Engineering team. As a DV Engineer at NVIDIA's GPU-Networking group, you'll make a real impact in a dynamic, technology-focused company while being a part of the team that develops the flagship product of todays’ semiconductor industry – NVIDIA’s GPU Super-Chip. What you’ll be doing: • Work in a DV (Design Verification) team that has a global responsibility over deliverable units and clusters to the silicon GPU • Integrations and Full-Chip models • Verification of chip blocks/entities according to specifications under challenging constraints • Your daily work will involve all aspects of Design Verification : Planning, Coding, Coverage and Integration What we need to see: • 3+ years of experience in RTL design verification. • B.Sc. in Electrical Engineering or Computer Engineering. • A team player with good communication and interpersonal skills. Ways to stand out from the crowd: • Background in Specman and System-Verilog UVM • Knowledge in Networking NVIDIA has some of the most forward-thinking and hardworking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Come join our team and help us build the future HPC and data centers. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer.

NVIDIA is seeking a passionate Senior Software Engineer to join our embedded processing software SDK development team. We are seeking hardworking and experienced engineers to contribute to the development of advanced networking and embedded processing software. You will be part of a team developing next-generation embedded processor SW, working closely with other SW R&D teams and SW Architects. What you will be doing: • Design and develop advanced features for our world-class embedded processing • Write clean, efficient, and maintainable code using advanced AI-based tools • Collaborate with team members, SW R&D, Architects, compiler team, and FW What we need to see: • B.Sc. degree or equivalent experience in Computer Science / Software Engineering • 5+ years of experience • Proficient knowledge and experience in C for an embedded environment • Strong design, coding, analytical, debugging, and problem-solving skills • Full ownership & end-to-end responsibility • Excellent social and written communication skills Ways To Stand Out From The Crowd: • Can do attitude, independency and agility • Ability to quickly adapt to new technology and go deep into new areas • Knowledge of embedded processing, especially with the RISC-V processor, is an advantage • Knowledge of Linux kernel and driver development is an advantage NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you! NVIDIA is committed to fostering a diverse work environment and is proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) based on race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.