Verification Engineer jobs in Israel

Overview Microsoft is building the fastest and most reliable networks for AI and cloud data centers. Microsoft Azure is one of the largest public cloud platforms worldwide, providing a great channel for product impact that touches the lives of millions of users daily. Microsoft’s partnership with world leaders in AI technology provides unparalleled opportunities for innovation at the cutting edge of high-performance computing and networking. Our team has delivered Azure Boost to production through 2 generations and we are now looking for talented hardware design engineers to join our team, developing Azure’s next generation networking devices.  Microsoft’s innovative approach for hardware/software co-design leverages custom-designed hardware to offload and accelerate many types of computations and functions of the Azure network. Our vertical work environment offers an unparalleled opportunity to define end-to-end features, implement & test them, participate in their deployment in the cloud, and see your work used on a global scale! Come join us and be challenged daily as you build advanced hardware/software acceleration solutions for some of the world’s largest datacenter networks and AI supercomputers. This is a great opportunity to join a team that has built some of the largest scale cloud systems ever deployed and learn from the very best. Responsibilities • Design verification environments for units and full devices, based on deep understanding of customer requirements, DUT functionality, and system architecture. • Design and implement VIP, constrained-random testbenches, assertions, coverage, and verification infrastructure using SystemVerilog/UVM. • Develop and execute test/coverage plans to verify hardware designs and reach cloud-grade quality. • Work closely with architects, RTL designers, firmware/software engineers, and validation teams throughout the design and verification lifecycle • Debug complex design and verification failures, perform root-cause analysis, and collaborate with design and architecture teams to drive issues to closure. Qualifications • At least 4 years of proven experience in verification of large ASIC/FPGA designs  • BSc/MSc in Electrical Engineering, Computer Science, or Computer Engineering, from a major university.  Other • Proven knowledge of hardware verification concepts and tools (UVM, unit level and full chip verification, coverage-based verification) • A versatile can-do, problem-solving attitude, and desire to handle a wide array of challenges.  • Proven communication skills in English. • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:• Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter #azurecorejobs #azurehardwarejobsil This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Description Wiliot was founded by the team that invented one of the technologies at the heart of 5G. Their next vision was to develop an IoT sticker, a computing element that can power itself by harvesting radio frequency energy, bringing connectivity and intelligence to everyday products and packaging, things previously disconnect from the IoT. This revolutionary mixture of cloud and semiconductor technology is being used by some of the world’s largest consumer, retail, food and pharmaceutical companies to change the way we make, distribute, sell, use and recycle products. Our investors include Softbank, Amazon, Alibaba, Verizon, NTT DoCoMo, Qualcomm and PepsiCo. Wiliot is looking for a talented and experienced engineer to take part in the verification efforts for the company’s core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path. Responsibilities: • Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration. • Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality. Responsibilities • Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration. • Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality. Requirements • Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience. • 2+ years in design verification, with strong SV/UVM proficiency (Less experienced engineers with high university grades or vast knowledge in RTL design will also be considered) • Self-motivated, ability to work, lead and drive tasks to completion. • Great interpersonal skills. • Understanding of digital ASIC design flows and SoC development methodologies. experience with SoC/full-chip verification, simulation/debug tools, and Unix/Linux environments, scripting languages (Python, etc.) and version control. Advantages • Knowledge in Low Power techniques and UPF standard. • Knowledge in Mix signals SoCs. • Experience with SW/HW Co-development #LI-Hybrid

Mobileye’s Unit Level Verification Team in Haifa is looking for an experienced verification engineer to be involved in the development of Mobileye’s future AI and deep learning HW accelerators. This is an exciting opportunity to join a team of highly talented engineers, working on the most cutting-edge technologies to deliver Mobileye’s EyeQ future chips, aimed to power the world’s first fully Autonomous Vehicle! What will your job look like: • Define, implement and enhance verification environments using UVM methodology. • Write and debug tests that combine UVM methodology and SW code. • Identify and write various types of coverage measures. • Collaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment. • Integrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs. All you need is: • BSc in electrical engineering, computer engineering, or computer science. • 4 years of experience working in verification environment, tests, and test bench development (SV/UVM/C/C++). • System Verilog writing skills, preferably in OVM/UVM. • SW embedded experience, C/C++ skills. • TestPlan defining and Coverage-Driven Verification experience. • 3rd-party IPs integration testing experience. • Waveform debugging with the latest EDA tools, root-cause bugs independently. Nice to have: • Skills in scripting Perl/Python. • Knowledge in Industry Standard protocols such as AXI/OCP/APB. Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

Mobileye’s Unit Level Verification Team in Haifa is looking for an experienced verification engineer to be involved in the development of Mobileye’s future AI and deep learning HW accelerators. This is an exciting opportunity to join a team of highly talented engineers, working on the most cutting-edge technologies to deliver Mobileye’s EyeQ future chips, aimed to power the world’s first fully Autonomous Vehicle! What will your job look like: • Define, implement and enhance verification environments using UVM methodology. • Write and debug tests that combine UVM methodology and SW code. • Identify and write various types of coverage measures. • Collaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment. • Integrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs. All you need is: • BSc in electrical engineering, computer engineering, or computer science. • 8+ years of experience working in verification environment, tests, and test bench development (SV/UVM/C/C++). • System Verilog writing skills, preferably in OVM/UVM. • SW embedded experience, C/C++ skills. • TestPlan defining and Coverage-Driven Verification experience. • 3rd-party IPs integration testing experience. • Waveform debugging with the latest EDA tools, root-cause bugs independently. Nice to have: • Skills in scripting Perl/Python. • Knowledge in Industry Standard protocols such as AXI/OCP/APB. Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

Mobileye’s Unit Level Verification Team in Haifa is looking for an experienced verification engineer to be involved in the development of Mobileye’s future AI and deep learning HW accelerators. This is an exciting opportunity to join a team of highly talented engineers, working on the most cutting-edge technologies to deliver Mobileye’s EyeQ future chips, aimed to power the world’s first fully Autonomous Vehicle! What will your job look like: • Define, implement and enhance verification environments using UVM methodology. • Write and debug tests that combine UVM methodology and SW code. • Identify and write various types of coverage measures. • Collaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment. • Integrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs. All you need is: • BSc in electrical engineering, computer engineering, or computer science. • 8+ years of experience working in verification environment, tests, and test bench development (SV/UVM/C/C++). • System Verilog writing skills, preferably in OVM/UVM. • SW embedded experience, C/C++ skills. • TestPlan defining and Coverage-Driven Verification experience. • 3rd-party IPs integration testing experience. • Waveform debugging with the latest EDA tools, root-cause bugs independently. Nice to have: • Skills in scripting Perl/Python. • Knowledge in Industry Standard protocols such as AXI/OCP/APB. Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

Description verificationQuantum Machines is a global leader in control systems for quantum computing, a field on the verge of exponential growth. Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands. At the core of QM lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers. Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field. We are looking for a Verification Engineer who embodies ambition and positivity, who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfil the evolving needs of our expanding customer base. The Verification engineer we look for will be a highly talented and motivated person, who is a real team player and can collaborate closely with engineers from other disciplines and quantum physicists. Responsibilities: • Practicing the full range of verification aspects • Creating a verification environment from scratch (drivers, monitors, coverage...) • VIP (DDR/PCIe/AXI) integration • Defining verification sequences via a complex control-flow constraint set • System understanding of a full-stack product with strong HW-SW coupling • Reference model integration • Test plan definition • Defining verification flows and creating the proper infrastructure to support it Requirements Requirements: • At least 5 years of experience. • Ability to ramp up verification environments from scratch • Experience with UVM, System Verilog - Advantage • Knowledge of Verification IPs and protocols (PCIe, DDR, AXI) • Good understanding of HW/SW interaction- Advantage • Knowledge in C/C++/Python/System C - Advantage

Description Quantum Machines is a global leader in control systems for quantum computing, a field on the verge of exponential growth. Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands. At the core of QM lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers. Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field. We are looking for a Verification Engineer who embodies ambition and positivity, who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfil the evolving needs of our expanding customer base. The Verification engineer we look for will be a highly talented and motivated person, who is a real team player and can collaborate closely with engineers from other disciplines and quantum physicists. Responsibilities: • Practicing the full range of verification aspects • Creating a verification environment from scratch (drivers, monitors, coverage...) • VIP (DDR/PCIe/AXI) integration • Defining verification sequences via a complex control-flow constraint set • System understanding of a full-stack product with strong HW-SW coupling • Reference model integration • Test plan definition • Defining verification flows and creating the proper infrastructure to support it Requirements • 3- 5 years of experience with UVM, System Verilog. • Ability to ramp up verification environments from scratch. • Knowledge of Verification IPs and protocols (PCIe, DDR, AXI). • Good understanding of HW/SW interaction- Advantage • Knowledge in C/C++/Python/System C - Advantage