Verification Engineer jobs in Israel

Description NextSilicon is reimagining high-performance computing (HPC & AI). Our accelerated compute solutions leverage intelligent adaptive algorithms to vastly accelerate supercomputers, driving them forward into a new generation. We have developed a novel software-defined hardware architecture that is achieving significant advancements in both the HPC and AI domains. At NextSilicon, everything we do is guided by three core values: • Professionalism: We get exceptional results through professionalism and unwavering dedication to quality and performance. • Unity: Collaboration is key to success; we foster a work environment where every employee feels valued and heard. • Impact: We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide. We are looking for a talented and experienced engineer to take part in the verification efforts for the company’s core product. This position involves building a complex verification environment from scratch, and defining and executing a test plan. In this role, you will be leading verification from A to Z and will have a critical impact on the company. Requirements • 6+ years of verification experience, including hands-on experience building complex environments from scratch • Advanced knowledge of verification flow, SOC architecture and design • Expertise in verification languages such as SystemVerilog, UVM, Spaceman • Knowledge of industry standard tools, including Verilog, Verilog simulator, and debug • Clear understanding of constrained random verification process, functional coverage, code coverage, and assertion methodology and philosophy • Bachelor degree in electrical engineering or computer science, or equivalent experience Responsibilities • Review specifications and develop attributes, tests, and coverage plans • Define methodology and test benches • Work closely with the verification team to ensure the quality of the product • Build and maintain a smart and scalable verification environment that ties into various systems • Work with the software, design, and micro-architecture teams to understand the functional and performance goals of the product’s design

Overview Microsoft is building the fastest and most reliable networks for AI and cloud data centers. Microsoft Azure is one of the largest public cloud platforms worldwide, providing a great channel for product impact that touches the lives of millions of users daily. Microsoft’s partnership with world leaders in AI technology provides unparalleled opportunities for innovation at the cutting edge of high-performance computing and networking. Our team has delivered Azure Boost to production through 2 generations and we are now looking for talented hardware design engineers to join our team, developing Azure’s next generation networking devices.  Microsoft’s innovative approach for hardware/software co-design leverages custom-designed hardware to offload and accelerate many types of computations and functions of the Azure network. Our vertical work environment offers an unparalleled opportunity to define end-to-end features, implement & test them, participate in their deployment in the cloud, and see your work used on a global scale! Come join us and be challenged daily as you build advanced hardware/software acceleration solutions for some of the world’s largest datacenter networks and AI supercomputers. This is a great opportunity to join a team that has built some of the largest scale cloud systems ever deployed and learn from the very best. Responsibilities • Design verification environments for units and full devices, based on deep understanding of customer requirements, DUT functionality, and system architecture. • Design and implement VIP, constrained-random testbenches, assertions, coverage, and verification infrastructure using SystemVerilog/UVM. • Develop and execute test/coverage plans to verify hardware designs and reach cloud-grade quality. • Work closely with architects, RTL designers, firmware/software engineers, and validation teams throughout the design and verification lifecycle • Debug complex design and verification failures, perform root-cause analysis, and collaborate with design and architecture teams to drive issues to closure. Qualifications • At least 4 years of proven experience in verification of large ASIC/FPGA designs  • BSc/MSc in Electrical Engineering, Computer Science, or Computer Engineering, from a major university.  Other • Proven knowledge of hardware verification concepts and tools (UVM, unit level and full chip verification, coverage-based verification) • A versatile can-do, problem-solving attitude, and desire to handle a wide array of challenges.  • Proven communication skills in English. • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:• Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter #azurecorejobs #azurehardwarejobsil This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Description For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Verification Team-Leader to be driving into the complicated RTL design verification activity on various design aspects. Requirements Key Responsibilities • Lead, mentor, and manage a team of verification engineers to meet project milestones and deliverables. • Define and execute verification strategies and plans for complex digital blocks and systems. • Oversee the development of robust and reusable verification environments using SystemVerilog and UVM. • Review and approve verification plans, testbenches, and coverage metrics. • Drive functional and coverage-based verification across multiple block/system verification cycles. • Collaborate with design engineers to debug and resolve functionality issues. • Ensure effective resource allocation and project planning to achieve optimal results. • Foster a culture of technical excellence, continuous learning, and innovation within the team. • Report verification progress, issues, and risks to senior management and other stakeholders. Required Qualifications • 8+ years of experience in digital design verification—a must. • 3+ years of experience managing or leading verification teams. • Proven track record of completing two or more full block/system verification cycles. • In-depth knowledge of VLSI verification flows, concepts, and methodologies. • Expertise in verification using SystemVerilog, UVM, or other industry-standard methodologies (eRM, OVM). • Experience with data protocols or data path designs (Ethernet experience preferred). • Experience with Ai, agent build, integration to flow and shorten verification cycle time. • Strong problem-solving skills and the ability to debug complex functionality issues. • Excellent leadership, communication, and organizational skills to manage and inspire a team. Preferred Qualifications • Hands-on experience with high-speed communication protocols like Ethernet, PCIe, or SerDes. • Proficiency in scripting languages (e.g., Python, Perl) for automation of verification processes. • Familiarity with formal verification techniques and tools. • Background in system-level verification or post-silicon validation. • Experience with project planning tools and methodologies for effective team management.

Description For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Senior Verification Engineer to be driving into the complicated RTL design verification activity on various design aspects. Requirements Key responsibilities: • Ownership of block\cluster verification end to end from scratch. • Lead efforts of test bench architecture, Vplan definition and functional coverage. • Work closely with the design, architecture, algo teams and other stakeholders. • Support other team members and mentor less experienced engineers. Requirements • 10+ years of experience – a must • Performed at last 2 or more full block/system verification cycles. • In depth knowledge in VLSI verification flow, languages and concepts. • Experience in data path or data protocols, specifically Ethernet - preferred • Verification using one of the known methodologies (eRM, UVM, OVM). Responsibilities • Plan and perform the verification of digital design blocks according to the design specification and interacting with design engineers. • Build verification environments using SystemVerilog and UVM. • Identify and write all types of coverage measures for corner-cases. • Debug the functionality with design engineers. • Perform coverage collection and follow the metrices to close the full functionality.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters. As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You won’t just execute tasks; you will define the Formal verification strategy for chips that drive the world’s largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications. Key Responsibilities • Own and develop formal verification environments from scratch through to sign-off • Apply formal verification methodologies and strategies to prove the correctness of intricate designs • Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements • Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs • Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently • Architect and develop generic, common formal functions and properties to be reused across multiple projects Basic Qualifications • Bachelor's degree in Electrical Engineering or a related technical field • 4+ years of hands-on experience in Formal Verification within semiconductor companies • Deep expertise in formal verification methodologies, tools, and flows • Strong understanding of RTL design and verification principles • Experience with industry-standard formal verification tools (Jasper, VC Formal, or similar) • Excellent communication skills, strong analytical thinking, and a proactive, "can-do" approach to problem-solving Preferred Qualifications • Track record of successfully taking complex blocks or subsystems through the entire formal verification lifecycle • Experience with SystemVerilog UVM-based design verification • Knowledge of networking standards (Ethernet, NVLink, UALink, PCIe) • Background in high-speed serial interface verification We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Job Details: Job Description: We're looking for talented, self-motivated engineers to join our Design Verification (DV) team in a junior or mid-level position. We work on some of the most technically challenging silicon in the industry, spanning digital and analog design, DSP pipelines, and firmware-hardware co-verification. What We Build Our team develops and verifies high-speed SerDes IP, the physical layer technology that moves data at speeds from 10Gbps to 100Gbps+ across PCIe, Ethernet, and other industry-standard interfaces. Getting this right matters, the world's data moves through what we build. What You'll Work On • Constrained-random and coverage-driven verification of complex high-speed SerDes mixed-signal IP, including advanced verification environment development • Validation of DSP datapaths • FW/HW joint verification • Leveraging AI-assisted tools as a core part of your daily engineering workflow What We're Looking For • Bachelor's degree in EE, CE, or CS — recent graduate with a strong academic record • Solid grasp of digital design, computer architecture, and software programming • Analytical mindset — you enjoy root-causing problems, not just finding them • Ability to thrive in a dynamic, multi-disciplinary environment • Hands-on exposure to SystemVerilog/UVM or Python — a significant advantage, but not required What We Offer • A collaborative and innovative environment where great ideas come from every level of the team • A great place to work — we take the work seriously, and each other's success personally • Exposure to the full verification lifecycle — from spec to tape-out sign-off • A team culture that embraces modern tooling, including AI-assisted engineering, as a competitive advantage • A real growth path from day one Qualifications: • Bachelor's degree in electrical engineering, Computer Engineering, or Computer Science • 0–3 years of industry or academic experience in hardware design or verificationNice to Have • Hands-on experience with SystemVerilog/UVM • Python scripting for verification automation • Familiarity with mixed-signal or analog simulation concepts • Knowledge of high-speed protocols such as PCIe or Ethernet • Prior internship or experience in RTL design or verification • Strong academic record; top graduating students are encouraged to apply Job Type: Regular Shift: Shift 1 (Israel) Primary Location: Jerusalem, Israel Additional Locations: Haifa, Israel, TLV Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Meet the Team We are a leading Design for Test (DFT) group, delivering end-to-end solutions for Cisco’s flagship products, including Cisco Silicon One. Our chips are strategically placed in critical AI infrastructure, powering next-generation network devices and supporting advanced AI workloads. We push the boundaries of technology by developing innovative DFT solutions that drive industry-leading programmability, scalability, test quality, and performance. Our team operates in a hybrid model, with three days a week in the office in Midtown Tel Aviv or Caesarea, fostering collaboration and technical excellence in a startup-like atmosphere within a stable, global corporation. Role Focus: We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the Cisco SiliconOne DFT team. This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon. Your Impact Lead and drive DFT verification activities within the Cisco SiliconOne DFT team. Develop verification plans, environments, checkers, assertions, and coverage models for DFT features. Verify DFT architecture and implementation in close collaboration with DFT, design, architecture, and verification teams. Work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features. Debug complex pre-silicon issues across RTL, verification environments, and DFT logic. Contribute to scalable methodologies, reusable verification components, and best practices for DFT DV. Help bridge between general DV methodologies and DFT-specific design and verification needs. Minimum Qualifications • B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field. • 5+ years of experience in design verification roles. • Strong experience with SystemVerilog and UVM-based verification environments. • Experience developing verification plans, coverage models, assertions, and debug flows. • Strong communication skills and ability to work closely with cross-functional teams. • Motivation to learn DFT concepts and become a key contributor in the DFT DV domain. Preferred Qualifications • Familiarity with DFT concepts such as scan insertion, memory BIST, ATPG, boundary scan, and silicon test flows. • Experience with complex SoC verification, networking silicon, or high-performance AI-driven silicon. • System-level understanding of large-scale chip architecture and integration. • Ability to build new methodologies and establish verification activity from the ground up. • High attention to detail, ownership mindset, and willingness to grow into new technical domains. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Speedata is modernizing analytics infrastructure with the first purpose-built ASIC processor, the Analytics Processing Unit (APU), for analytics and AI data workloads. Delivering up to 100x faster Apache Spark performance while cutting infrastructure TCO by 90%, the APU executes analytics operations directly in silicon with seamless integration and no code changes. Job Description We are looking for highly motivated engineers who love the challenges and the opportunity of a small company. Join us and be a part of a small and dynamic team, which revolutionizes the parallel processor architecture. Qualifications BSc in Electronics Engineering or Computer Science 10+ Years of industry experience in verification, full chip dev. cycle. 2+ years of experience in leading a team of engineers (including technical and personal mentoring, etc.) Experience with System Verilog and UVM methodology - MUST Advantages M.Sc. in Electronics Engineering or Computer Science Working experience with Formal verification Scripting skills in Python/Perl/shell Hands-on experience with two or more of the following :PCIE (Gen5 and above).DDR (v4 and above).AMBA protocol family, (inc. AXI4+, ACE/CHI)ARM core architecture.

Speedata is modernizing analytics infrastructure with the first purpose-built ASIC processor, the Analytics Processing Unit (APU), for analytics and AI data workloads. Delivering up to 100x faster Apache Spark performance while cutting infrastructure TCO by 90%, the APU executes analytics operations directly in silicon with seamless integration and no code changes. Job Description We are looking for highly motivated engineers who love the challenges and the opportunity of a small company. Join us and be a part of a small and dynamic team, which revolutionizes the parallel processor architecture. Qualifications BSc in Electronics Engineering or Computer Science 10+ Years of industry experience in verification, full chip dev. cycle. Experience with System Verilog and UVM methodology - MUST Advantages M.Sc. in Electronics Engineering or Computer Science Working experience with Formal verification Scripting skills in Python/Perl/shell Hands-on experience with two or more of the following: PCIE (Gen5 and above). DDR (v4 and above). AMBA protocol family, (inc. AXI4+, ACE/CHI) ARM core architecture.

Description Wiliot was founded by the team that invented one of the technologies at the heart of 5G. Their next vision was to develop an IoT sticker, a computing element that can power itself by harvesting radio frequency energy, bringing connectivity and intelligence to everyday products and packaging, things previously disconnect from the IoT. This revolutionary mixture of cloud and semiconductor technology is being used by some of the world’s largest consumer, retail, food and pharmaceutical companies to change the way we make, distribute, sell, use and recycle products. Our investors include Softbank, Amazon, Alibaba, Verizon, NTT DoCoMo, Qualcomm and PepsiCo. Wiliot is looking for a talented and experienced engineer to take part in the verification efforts for the company’s core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path. Responsibilities: • Lead the full verification lifecycle and methodologies. Plan, Design and Execute verification of SV/UVM Block level and Full chip environments , creating and execution test plans, tracking progress, and ensuring verification closure across diverse Mix-signals SoC simulation using Verilog, MATLAB, HW/SW Co-simulation and lab integration. • Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality. Responsibilities • Lead the full verification lifecycle and methodologies. Plan, Design and Execute verification of SV/UVM Block level and Full chip environments , creating and execution test plans, tracking progress, and ensuring verification closure across diverse Mix-signals SoC simulation using Verilog, MATLAB, HW/SW Co-simulation and lab integration. • Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality. Requirements • Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience. • 5+ years in design verification, with strong SV/UVM proficiency (Less experienced engineers with high university grades or vast knowledge in RTL design will also be considered) • Self-motivated and able to lead and drive tasks to completion. • Great interpersonal skills. • Understanding of digital ASIC design flows and SoC development methodologies. experience with SoC/full-chip verification, simulation/debug tools, Unix/Linux environments, scripting languages (Python, etc.) and version control. Advantages • Knowledge in Low Power Verification and UPF standard. • Knowledge in Mix signals SoCs. • Experience with SW/HW Co-development #LI-Hybrid

Description Wiliot was founded by the team that invented one of the technologies at the heart of 5G. Their next vision was to develop an IoT sticker, a computing element that can power itself by harvesting radio frequency energy, bringing connectivity and intelligence to everyday products and packaging, things previously disconnect from the IoT. This revolutionary mixture of cloud and semiconductor technology is being used by some of the world’s largest consumer, retail, food and pharmaceutical companies to change the way we make, distribute, sell, use and recycle products. Our investors include Softbank, Amazon, Alibaba, Verizon, NTT DoCoMo, Qualcomm and PepsiCo. Wiliot is looking for a talented and experienced engineer to take part in the verification efforts for the company’s core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path. Responsibilities: • Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration. • Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality. Responsibilities • Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration. • Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality. Requirements • Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience. • 2+ years in design verification, with strong SV/UVM proficiency (Less experienced engineers with high university grades or vast knowledge in RTL design will also be considered) • Self-motivated, ability to work, lead and drive tasks to completion. • Great interpersonal skills. • Understanding of digital ASIC design flows and SoC development methodologies. experience with SoC/full-chip verification, simulation/debug tools, and Unix/Linux environments, scripting languages (Python, etc.) and version control. Advantages • Knowledge in Low Power techniques and UPF standard. • Knowledge in Mix signals SoCs. • Experience with SW/HW Co-development #LI-Hybrid

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Join a highly skilled development team, driving the development of Marvell's next-generation network switches. Our team is responsible for a wide range of IPs for switching products, from initial definition through architecture, design, and verification. As an intern, you will learn switch architecture, design and verification development tools and modern methodologies. You will be doing hands-on development tasks and learn to become an experienced engineer. You will learn system verilog, UVM, Python, C++, using AI tools, and how to implement and verify complex features. You will investigate and implement new protocols and features and verify them to tapeout quality. We are looking for excellent students, able to handle complex problems, with excellent people relations and collaboration skills. What You Can Expect • Implement new design and verification features. • Reach high-frequency, high-performance, and low-power targets. • Write a verification test plan using random techniques and coverage analysis. • Develop a complex object-oriented random verification environment using System Verilog/UVM. • Create tests and tune the environment to achieve coverage goals. • Own and debug failures in simulation to root-cause problems. • Analysis/closure of code and functional coverage. • Use scripting languages to automate repetitive tasks and improve efficiency. What We're Looking For • Candidate pursuing a B.S. or M.S. degree in CS, EE, or a related technical field. • At least 1.5 years remaining until graduation. • Good understanding of object-oriented programming and digital logic. • Strong interpersonal skills and ability to work effectively in a team. • Excellent problem-solving skills. 

Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-SJ1

Mobileye SOC verification group owns the important and challenging job of verifying Mobileye's chip. It is involved from product specification to final SOC delivery, and involves all the system components. The group is made up of few of the best verification engineers, so besides contributing to making our roads safer, you’ll get the chance to work at one of the most professional verification teams. What will your job look like: • You'll be responsible for Pre-Silicon system-level verification of the most cutting-edge AI accelerators and technologies in the automotive field. • Define the TestPlan, develop and run tests on simulation/emulation environments, develop test environment and verification collaterals. • You'll have a broad effect on our unique product from the very beginning of the process. All you need is: • BSc in electrical engineering, computer engineering or computer science. • 7+ years of experience working in verification environment, tests, and test bench development (C/C++/SV). • TestPlan defining and Coverage-Driven Verification experience. • Fullchip/SOC verification experience, strong system understanding. • Good debug capabilities using the latest EDA tools. • Knowledge in Industry Standard protocols such as AXI/ACEL/OCP/CHI. Nice to have: • SW embedded experience, C/C++ skills. • Strong skills in scripting Perl/Python. • System Verilog writing skills, preferably in OVM/UVM. • 3rd-party IPs integration testing experience. Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

Mobileye’s Unit Level Verification Team in Haifa is looking for an experienced verification engineer to be involved in the development of Mobileye’s future AI and deep learning HW accelerators. This is an exciting opportunity to join a team of highly talented engineers, working on the most cutting-edge technologies to deliver Mobileye’s EyeQ future chips, aimed to power the world’s first fully Autonomous Vehicle! What will your job look like: • Define, implement and enhance verification environments using UVM methodology. • Write and debug tests that combine UVM methodology and SW code. • Identify and write various types of coverage measures. • Collaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment. • Integrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs. All you need is: • BSc in electrical engineering, computer engineering, or computer science. • 8+ years of experience working in verification environment, tests, and test bench development (SV/UVM/C/C++). • System Verilog writing skills, preferably in OVM/UVM. • SW embedded experience, C/C++ skills. • TestPlan defining and Coverage-Driven Verification experience. • 3rd-party IPs integration testing experience. • Waveform debugging with the latest EDA tools, root-cause bugs independently. Nice to have: • Skills in scripting Perl/Python. • Knowledge in Industry Standard protocols such as AXI/OCP/APB. Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

Mobileye’s Unit Level Verification Team in Haifa is looking for an experienced verification engineer to be involved in the development of Mobileye’s future AI and deep learning HW accelerators. This is an exciting opportunity to join a team of highly talented engineers, working on the most cutting-edge technologies to deliver Mobileye’s EyeQ future chips, aimed to power the world’s first fully Autonomous Vehicle! What will your job look like: • Define, implement and enhance verification environments using UVM methodology. • Write and debug tests that combine UVM methodology and SW code. • Identify and write various types of coverage measures. • Collaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment. • Integrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs. All you need is: • BSc in electrical engineering, computer engineering, or computer science. • 8+ years of experience working in verification environment, tests, and test bench development (SV/UVM/C/C++). • System Verilog writing skills, preferably in OVM/UVM. • SW embedded experience, C/C++ skills. • TestPlan defining and Coverage-Driven Verification experience. • 3rd-party IPs integration testing experience. • Waveform debugging with the latest EDA tools, root-cause bugs independently. Nice to have: • Skills in scripting Perl/Python. • Knowledge in Industry Standard protocols such as AXI/OCP/APB. Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

Mobileye’s Unit Level Verification Team in Haifa is looking for an experienced verification engineer to be involved in the development of Mobileye’s future AI and deep learning HW accelerators. This is an exciting opportunity to join a team of highly talented engineers, working on the most cutting-edge technologies to deliver Mobileye’s EyeQ future chips, aimed to power the world’s first fully Autonomous Vehicle! What will your job look like: • Define, implement and enhance verification environments using UVM methodology. • Write and debug tests that combine UVM methodology and SW code. • Identify and write various types of coverage measures. • Collaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment. • Integrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs. All you need is: • BSc in electrical engineering, computer engineering, or computer science. • 4 years of experience working in verification environment, tests, and test bench development (SV/UVM/C/C++). • System Verilog writing skills, preferably in OVM/UVM. • SW embedded experience, C/C++ skills. • TestPlan defining and Coverage-Driven Verification experience. • 3rd-party IPs integration testing experience. • Waveform debugging with the latest EDA tools, root-cause bugs independently. Nice to have: • Skills in scripting Perl/Python. • Knowledge in Industry Standard protocols such as AXI/OCP/APB. Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

Mobileye SOC verification group owns the important and challenging job of verifying Mobileye's chip. It is involved from product specification to final SOC delivery, and involves all the system components. The group is made up of few of the best verification engineers, so besides contributing to making our roads safer, you’ll get the chance to work at one of the most professional verification teams. What will your job look like: • You'll be responsible for Pre-Silicon system-level verification of the most cutting-edge AI accelerators and technologies in the automotive field. • Define the TestPlan, develop and run tests on simulation/emulation environments, develop test environment and verification collaterals. • You'll have a broad effect on our unique product from the very beginning of the process. All you need is: • BSc in electrical engineering, computer engineering or computer science. • 7+ years of experience working in verification environment, tests, and test bench development (C/C++/SV). • TestPlan defining and Coverage-Driven Verification experience. • Fullchip/SOC verification experience, strong system understanding. • Good debug capabilities using the latest EDA tools. • Knowledge in Industry Standard protocols such as AXI/ACEL/OCP/CHI. Nice to have: • SW embedded experience, C/C++ skills. • Strong skills in scripting Perl/Python. • System Verilog writing skills, preferably in OVM/UVM. • 3rd-party IPs integration testing experience. Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

The Mobileye Automated Driving Hardware group in Haifa is looking for an Experienced Formal Verification Engineer to join a team of talented engineers developing next-generation silicon for autonomous driving platforms. This is a unique opportunity to enter one of the most challenging and rewarding disciplines in hardware development. Formal Verification combines deep understanding of computer architecture, digital design, and advanced verification methodologies to prove hardware correctness and uncover bugs that traditional testing may never find. What will your job look like: • Be the owner of formal verification environment from first draft to sign-off stage. • Apply formal methods to verify the correctness of various complex digital systems. • Work with HW architects\designers to define assumptions, rules and cover properties. • Help define the formal verification methodology and environment to be applied by the team. • Explore new Formal methods and Tools. • Work with tools like Cadence JasperGold, Verisium manager, Xcelium, Indago. • Analyze verification results, identify bugs, and collaborate with engineers to resolve design issues. • Develop generic formal blocks\functions of commonly used logic, to be later used off the shelf. All you need is: • BSc in electrical engineering, computer engineering, or computer science. • Passion for the field of Formal Verification. • 5+ years of experience in Formal Verification. • Experience coding system-verilog hardware description language. • Experience with scripting languages (e.g. python, tcl ). • Strong analytical and problem solving skills. • Ability to work independently and in a team-oriented environment. Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

We are now looking for a Chip Design Verification Engineer. NVIDIA is seeking a verification engineer to join the chip design methodologies team. The team is in charge of the verification methodologies, shared code, training, and embracing new technologies. One of our main goals is to make sure that the team works in an efficient manner, and provides high-quality deliveries. This position offers the opportunity to have real impact in a dynamic, technology-focused company. What you'll be doing: • Develop shared verification code and solutions to be widely used by the chip design team. • Develop groundbreaking methodologies to create a flawless experience for verification engineers to keep the focus on new problems. • Collaborate with the design automation team to provide end-to-end solutions that combine verification, simulation, and automation. • Get in touch with EDA vendors to learn about cutting-edge tools/technology and apply them into our verification process. • Understand the design, define the verification scope, develop the verification infrastructure and verify the correctness of the design. • Collaborate with designers, verification specialists to accomplish your tasks. • Develop training sessions. What we need to see: • A Bachelor's Degree in Electrical Engineering or Computer Science. • 5+ years of relevant experience • Exposure to design and verification tools. • Strong interpersonal skills and ability & desire to innovate. Ways to stand out from the crowd: • Experience in Specman / System Verilog UVM. • Understanding simulation tools. • Experience in building test benches, evaluate coverage and debug simulation failures. NVIDIA has some of the most forward-thinking and hardworking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Come join our networking verification team and help us developing great products by raising the efficiency and the quality standard in our chip design team.

We are looking for a best-in-class Senior Full-Chip Verification Engineer with a strong infrastructure mindset to join NVIDIA's Networking Silicon team. In this role, you will be responsible for the development and verification of our next-generation NICs at the system level, while also driving the evolution of the simulation infrastructure powering our verification flows. You will contribute to the architecture of high-speed communication devices by driving full-chip verification execution for the networking solutions powering the world's most advanced data centers, in a meaningful, growing environment where you make a huge impact in a technology-focused company. What you'll be doing: • Simulation Infrastructure & Acceleration: Identify bottlenecks in the verification flow and engineer creative solutions - building frameworks, optimizing regressions, and accelerating simulation throughput through innovative tooling • Multi-Language Development: Work across a diverse technology stack (SystemVerilog/UVM, Specman, Python, C/C++, scripting) - writing code and solving problems at every layer, from RTL testbenches to infrastructure utilities and automation. • System-Level Debug & Analysis: Gain a strong understanding of chip micro-architecture and features, investigate, debug, and resolve cross-block issues to guarantee feature correctness and compliance • AI-Enhanced Development: Accelerate development by leveraging cutting-edge AI coding tools and frameworks - applied to both verification and infrastructure challenges. • Cross-Team Collaboration: Work closely with multiple teams within organizations such as Architecture, u-arch, Firmware and all units inside the NIC What we need to see: • Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience • 8+ years of experience in verification, HW simulation, or infrastructure development for silicon projects • Infrastructure mindset - a proven ability to enhance and scale the systems that drive verification: regression frameworks, simulation performance, tooling, and flow automation • Creativity and proactivity - an innovation mindset with a proactive approach to adopting new methodologies and coding tools to solve complex challenges • Strong debugging, problem-solving, and analytical skills • A team player with good communication and interpersonal skills Ways to stand out: • Experience leveraging AI tools for verification automation or infrastructure acceleration. • Experience working in multi-language environments