Physical Design Engineer jobs in Israel

NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance. • Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems. • Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification. • Taking part in flows development. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience. • 5+ years of experience in Physical Design. • Proven experience in RTL2GDS flows and methodologies. • Knowledge in physical design flows and methodologies (PNR, STA, physical verification). • Deep understanding of all aspects of Physical construction and Integration. • Strong background of Physical Design Verification methodology LVS/DRC. • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc). • Great teammate. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

NVIDIA is looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • You will be in charge of developing physical design, synthesis, STA and Logic eq methodologies for implementation of networking chips and SOCs. • Work closely with block owners. full Chip STA engineers and project managers to assure high quality and timely convergence. • Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips. • Additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience). • At least 2 years of relevant experience • Proficiency using Python, Perl, Tcl, Make scripting. • Expertise in analysing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes. • Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power required and implementing them through ECOs is required. • Knowledge in process variation effect modelling and experience in design convergence taking into account variations. • Successful track record of delivering designs to production is necessary. • Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role. Ways to stand out from the crowd: • Familiarity with synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Innovus/Tempus) • Experience in methodology definition / flow owner of synthesis / Place and Route/ STA steps is an advantage. • Great teammate. • Ownership, self-learning skills, and ability to work autonomously. NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry! #LI-Hybrid

NVIDIA is looking for outstanding STA (Static Timing Analysis) Physical Design Engineers to join our remarkable Networking team in Israel. Our team focuses on building the industry's top high-speed communication devices, providing the highest efficiency and minimal latency. As part of NVIDIA, you'll be working in a meaningful, growing, and highly professional environment where your contributions make a significant impact. If you are ambitious, innovative, and ready to compete on the cutting edge of technology, this is the perfect opportunity for you! What you'll be doing: • Perform advanced Static Timing Analysis (STA) at a chiplet and FC level. • Running Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation. • Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages. • Responsible for a full timing closer and quality approval from pre-layout STA model through signoff. What we need to see: • B.Sc. in Electrical Engineering or Computer Engineering. • 2-3 years of experience as an STA engineer. • Strong ability to quickly adapt to new technology and delve deeply into new areas. • Excellent communication skills and a proven ability to work effectively in a team environment. • Demonstrated drive to develop and implement new solutions. Ways to Stand Out From the Crowd: • Knowledge in physical build flows and methodologies (PNR, STA, physical verification). • Familiarity with Prime Time tool NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

NVIDIA is looking for best-in-class Physical Design Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you will be doing: • Physical design of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance. • Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems. • Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification. • Taking part inflows development. • Act as Partition/Unit level physical design technical leader and focal point. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering. • 5+ years of experience in physical design. • Proven experience in RTL2GDS flows and methodologies. • Knowledge in physical design flows and methodologies (PNR, STA, physical verification). • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). • Great teammate. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance. • Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems. • Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification. • Taking part in flows development. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience. • 5+ years of experience in Physical Design. • Proven experience in RTL2GDS flows and methodologies. • Knowledge in physical design flows and methodologies (PNR, STA, physical verification). • Deep understanding of all aspects of Physical construction and Integration. • Strong background of Physical Design Verification methodology LVS/DRC. • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc). • Great teammate. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

NVIDIA is looking for best-in-class Physical Design Power Engineer to join our outstanding Networking Silicon Power engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput, lowest latency and best Power! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you will be doing: • Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints. • Optimization involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes. • Power estimation and power modeling. What we need to see: • B.SC./ M.SC. or equivalent experience in Electrical Engineering/Computer Engineering. • 1+ years of experience in physical design and/or BE power optimization aspects. • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). • Native ability to leverage modern AI tools to accelerate engineering workflows, productivity, and problem-solving. • Knowledge in physical design flows and methodologies (PNR, STA, physical verification) is an advantage. • FE design experience is an advantage. • Excellent problem-solving, partnership, and interpersonal skills. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance. • Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems. • Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification. • Taking part inflows development. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent experience. • 1+ years of relevant experience. • Proven experience in RTL2GDS flows and methodologies. • Knowledge in physical design flows and methodologies (PNR, STA, physical verification). • Deep understanding of all aspects of Physical construction and Integration. • Knowledge in Physical Design Verification methodology LVS/DRC. • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). • Great teammate. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

NVIDIA is looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • You will be developing physical design, STA, Logic eq, Power Integrity flows and methodologies for implementation of networking chips and SOCs. • Work closely with block owners, full Chip STA engineers to assure high quality and timely convergence. • Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips. • Additional responsibilities include participating and developing flow and tool methodologies for timing analysis and closure, power and noise analysis, IR-drop, EM and back-end verification across multiple projects. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience). • 2+ years of fulltime relevant experience in the areas listed below. • Proven experience and strong knowledge in key technical domains, including: Physical Design, Backend CAD (Computer-Aided Design), STA (Static Timing Analysis) and Timing closure methodologies. • Familiarity with industry-standard tools like PrimeTime (STA) and PrimePower (Power Estimation). • Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role. • Strong sense of ownership, self-learning skills, and ability to work both independently and collaboratively with internal and global teams Ways to stand out from the crowd: • Experience in Signoff domains: STA (PrimeTime), Power Estimation (PrimePower), Power Integrity (RedHawk), Formal eq. (Formality) • Knowledge in Tcl/Perl/Python • Versatile • Great teammate NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry! #LI-Hybrid

NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • You will be in charge of developing full-chip physical design methodologies, Physical Verification development and support through all the projects, Tapeout activities for implementation of networking chips and SOCs. • Work closely with Full Chip Layout owners and block owners, project managers to assure high quality and timely convergence. • Come up with unique and creative solutions to the state of the art FCL physical design problems that are needed for our chips. • We expect you to run, debug, and approve Physical Verification flows across multiple projects, ensuring strict adherence to our high standards. • Participating and developing flow and tool methodologies for fullchip, physical design verification across multiple projects. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience). • You should have at least 5+ years of hands-on Full-chip layout and Physical Verification experience, demonstrating your proven expertise. • A strong background in Physical Verification methodology, including DRC / LVS / ANT / ERC / DFM in advanced process nodes is necessary. • Proficiency using Python, Tcl, Shell, Make scripting. • Experience in Linux environments. • AI tools orientation or alternatively a desire to learn. • Familiarity with physical build EDA tools, including Synopsys (ICC2/FC) and Cadence (Innovus). • Familiarity with Physical Verification tools: Synopsys (ICV), Siemens (Calibre) • Self-motivation, attention to detail, and good interpersonal skills. Ways to stand out from the crowd: • Experience with data collection and analysis • Experience in methodology definition / flow owner of Full-chip / Place and Route • Great teammate. • Ownership, self-learning skills, and ability to work autonomously. NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • Perform physical layout for full-chip level, integration, pinning and bump route • Work with block owners and project managers to assure high quality convergence in all layout aspects • You will be responsible for chip layout from the floorplanning stage through tape-out What we need to see: • An Electronics Engineer certificate or a B.Sc. in Electrical Engineering • You should have 5 years of hands-on Full-chip layout and Physical Verification experience, demonstrating your proven expertise. • A strong background in Physical Verification methodologies, including DRC, LVS, ANT, ERC, and DFM for advanced process nodes, is required • Knowledge in scripts' language: TCL, Unix and Shell • Experience in Linux environments • AI tools orientation or alternatively a desire to learn • Familiarity with physical build EDA tools, including Synopsys (ICC2/FC) and Cadence (Innovus) • Familiarity with Physical Verification tools: Synopsys (ICV), Siemens (Calibre) • Self-motivation, attention to detail and good interpersonal skills Ways to stand out from the crowd: • Experience in methodology definition / flow owner of Full-chip / Place and Route • Great teammate • Ownership, self-learning skills and ability to work autonomously NVIDIA is widely considered to be one of the tech world’s most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you're creative and autonomous, we want to hear from you.

NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance. • Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems. • Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification. • Taking part inflows development. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent experience. • 2+ years of relevant experience. • Proven experience in RTL2GDS flows and methodologies. • Knowledge in physical design flows and methodologies (PNR, STA, physical verification). • Deep understanding of all aspects of Physical construction and Integration. • Knowledge in Physical Design Verification methodology LVS/DRC. • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). • Great teammate. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

Job Details: Job Description: Our team is dedicated to optimizing Intel’s cutting-edge process technology to meet the rapidly evolving needs of next-generation silicon designs. Operating at the intersection of process and design development, we drive continuous innovation in both physical design and methodology. We partner closely with Core and SoC design teams worldwide to drive both process and product-level optimization - directly enabling Intel to deliver highly competitive, high-performance and low-power products. Role Overview As a Physical Design & PPA Optimization Engineer, you will play a key role in achieving best-in-class Power, Performance, and Area (PPA) for Intel IPs. You will be responsible for identifying optimization opportunities, developing physical design optimization methodologies, executing the full physical design flow to evaluate PPA landing zones on new Intel process technologies, and translating findings into actionable recommendations that influence strategic decision-making and product direction. Key Responsibilities • Define and implement DTCO experiments to evaluate the interaction between process technology and physical design implementation. • Define and develop design optimization methodologies across all physical design flow domains, such as placement, CTS, routing, and timing closure • Run the full PnR flow to evaluate new technology impacts on PPA metrics. • Identify trade-offs and optimization opportunities at the device, cell, and block Qualifications: Minimum Qualifications • BSc or MSc in Electrical Engineering, Computer Engineering, or a related field • Hands-on experience in physical or circuit design • Basic scripting experience using Python, Tcl, or a similar language • Strong analytical and problem-solving skills • Ability to analyze implementation results and communicate conclusions clearly Preferred Qualifications • 2+ years of experience in physical design or circuit design • Familiarity with physical design implementation flows and methodologies • Solid understanding of transistor, cell, and block-level PPA trade-offs • Experience developing physical design methodologies and analysis tools #LI-DL1 Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Haifa Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *