Physical Design Engineer jobs in Israel

Description For an exciting well-funded start-up, we are looking for a Backend Team member. You will work on complex design, high frequency and low-power budget. Work on ramp-up full RTL2GDSII flow for leading technology and work with external vendors. Requirements Key responsibilities: • RTL-to-GDSII Ownership: execute the complete backend implementation flow (Logic Synthesis, P&R, Tape-Out, IR-drop, etc.), ensuring timely, first-pass silicon success. · Constraints & Timing Closure: Work with design and DFT engineers to write timing and physical constraints, and sign-off on the design using comprehensive Static Timing Analysis (STA), timing eco implementation. · Advanced Physical Implementation: Drive complex physical design tasks including Floorplanning, Power/Ground (PG) Mesh implementation, and handling advanced clocking (CTS/Clock-Mesh) and Hierarchical Design flows. · Low Power Expertise: Define, implement, and verify advanced low power design techniques to meet aggressive power consumption targets. · Design for Manufacturability: Implement and verify Design-for-Test (DFT) strategies and close physical verification challenges, specifically focusing on IR-Drop analysis. · IP Integration & Automation: Execute complex IP integration, incorporating blocks generated by memory compilers and other automated tools. • Collaboration: work closely with design team to understand the data path and correctly implement the floorplan, provide feedback on RTL changes required, Implement logical eco post RTL freeze with design team. • CAD: Improve existing implementation flows to achieve better QOR, write scripts for supporting the P&R flows. Minimum Qualifications • Experience of 10+ years in backend design • Strong expertise of full RTL2GDSII including: • Logic synthesis & equivalence checking • Constraints definition and writing • Complicated IP integration • Memory compilers and other automated block generators • DFT • Floorplanning, PG Mesh • P&R • Low power design including definition, implementation and verification • Timing STA • IR-Drop • BS/MS in EE/CE from lead universities Preferred Qualifications • Team player • Highly motivated • Learning abilities • Good communication • Work with external vendors • Experience in Synopsys/Cadence tools is an advantage • Low power techniques • Clock-mesh/ multi source cts • Hierarchical design flow • Experience in tape-out procedures • RTL code reading A very interesting job and good conditions are guaranteed to the candidates

Description For an exciting well-funded start-up, we are looking for a Backend Team member. You will work on complex design, high frequency and low-power budget. Work on ramp-up full RTL2GDSII flow for leading technology and work with external vendors. Requirements Key responsibilities: • RTL-to-GDSII Ownership: execute the complete backend implementation flow (Logic Synthesis, P&R, Tape-Out, IR-drop, etc.), ensuring timely, first-pass silicon success. · Constraints & Timing Closure: Work with design and DFT engineers to write timing and physical constraints, and sign-off on the design using comprehensive Static Timing Analysis (STA), timing eco implementation. · Advanced Physical Implementation: Drive complex physical design tasks including Floorplanning, Power/Ground (PG) Mesh implementation, and handling advanced clocking (CTS/Clock-Mesh) and Hierarchical Design flows. · Low Power Expertise: Define, implement, and verify advanced low power design techniques to meet aggressive power consumption targets. · Design for Manufacturability: Implement and verify Design-for-Test (DFT) strategies and close physical verification challenges, specifically focusing on IR-Drop analysis. · IP Integration & Automation: Execute complex IP integration, incorporating blocks generated by memory compilers and other automated tools. • Collaboration: work closely with design team to understand the data path and correctly implement the floorplan, provide feedback on RTL changes required, Implement logical eco post RTL freeze with design team. • CAD: Improve existing implementation flows to achieve better QOR, write scripts for supporting the P&R flows. Minimum Qualifications • Experience of 5+ years in backend design • Strong expertise of full RTL2GDSII including: • Logic synthesis & equivalence checking • Constraints definition and writing • Complicated IP integration • Memory compilers and other automated block generators • DFT • Floorplanning, PG Mesh • P&R • Low power design including definition, implementation and verification • Timing STA • IR-Drop • BS/MS in EE/CE from lead universities Preferred Qualifications • Team player • Highly motivated • Learning abilities • Good communication • Work with external vendors • Experience in Synopsys/Cadence tools is an advantage • Low power techniques • Clock-mesh/ multi source cts • Hierarchical design flow • Experience in tape-out procedures • RTL code reading A very interesting job and good conditions are guaranteed to the candidates

NXP Israel teams are working on multiple fronts of complex SoC and new technologies development, which are at the main core technologies of NXP MCU business. We are looking for a Physical Design 9PD) Lead to join the Israel SoC team in our Yokneam site and lead the different complex SoC architecture that the team is planned to develop. At this position, you will be responsible for: • Lead a team of external and internal PD engineers. • In charge of all the PD activities of the project, Synthesis, PNR, PV, STA, etc.. • Work closely with the RTL team on SDC and UPF creations • Work with other teams at NXP like MSIP, CAD, Packing, etc. which are needed for the PD development Your Profile: • Minimum of 15 Years' experience. • Experience on SoC PD work for complex SoC. • Knowledge in all PD flows and tools. • Experience in working closely with different RTL, DV, MSIP, CAD and other teams. • Excellent communication skills and ability to work in parallel with different teams worldwide. • Independent and team player. • Knowledge of ultra-low power PD techniques. • Education: BsC in Electrical engineering, MsC is an advantage. More information about NXP in Israel... #LI-6710

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity. Key Responsibilities • Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments • Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence • Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments • Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners • Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient Basic Qualifications • B.Sc. in Electrical Engineering or Computer Engineering • 6+ years of hands-on experience in Static Timing Analysis (STA) at semiconductor companies, specifically working on advanced process technologies. (Note: Adjust years of experience based on the exact level you are targeting) • Deep expertise in multi-scenario STA, as well as timing and SDC constraint development and verification at the block and subsystem levels • Solid understanding of advanced margining methodologies, including OCV, AOCV, and POCV, from synthesis through to final sign-off • Solid knowledge of physical design flows (Synthesis, P&R, Physical Verification) and how they intersect with timing closure Preferred Experience • Experience developing and validating constraints using industry-standard tools like Timing Constraints Manager (Synopsys) or TimeVision (Ausdia) • Proven track record of executing STA on complex Macro-level designs and supporting Full-Chip timing integration • Strong background in scripting (Tcl, Python, Perl) and automation to enhance timing closure efficiency We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is a hyper-growth connectivity company building the purpose-built silicon that powers rack-scale AI infrastructure. As a Principal Physical Design Engineer and Team Lead in Israel, you will lead physical design teams that take complex, high-speed mixed-signal and digital SoCs from RTL handoff through tapeout. You will set the technical direction, drive execution across multiple projects, and grow the engineers around you, partnering closely with RTL, DFT, analog, and architecture teams. Your work will directly shape the performance, power, and area of products that connect the world's most demanding AI platforms. Key Responsibilities • Technical Leadership and Team Execution • Lead and mentor physical design engineers, setting priorities, assigning work, and ensuring high-quality, on-time delivery • Drive physical design projects end to end, including planning, scheduling, risk management, and status reporting • Define and evolve physical design methodologies, flows, and best practices across the team • Physical Implementation • Own block-level and top-level implementation: floorplanning, placement, clock tree synthesis, routing, and optimization • Drive timing closure, power integrity, and signal integrity to meet aggressive PPA targets in advanced process nodes • Lead physical verification and sign-off activities, including STA, IR/EM, DRC, LVS, and ECO management • Cross-Functional Collaboration • Partner with RTL design, DFT, analog, and architecture teams to resolve cross-domain implementation challenges early • Work with foundry, EDA vendors, and IP providers to ensure smooth tapeout and silicon bring-up • Contribute to hiring, onboarding, and professional development of team members Basic Qualifications • 10+ years of hands-on experience in physical design of complex SoCs or ASICs • Proven experience leading projects and technical teams through one or more full-chip tapeouts • Deep expertise with industry-standard physical design and sign-off tools (e.g., Cadence Innovus, Synopsys Fusion Compiler/ICC2, PrimeTime, Calibre) • Strong knowledge of timing closure, power/clock distribution, and physical verification in advanced process nodes • Excellent communication skills and the ability to work in a fully in-person, collaborative environment Preferred Qualifications • Experience with high-speed interface designs such as PCIe, Ethernet, or SerDes-based products • Proficiency in scripting languages such as Tcl, Python, or Perl for flow automation • Experience with hierarchical design, low-power methodologies, and ECO-driven closure • Demonstrated ability to mentor engineers and drive continuous improvement in team processes We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a Physical Design CAD Engineer with at least 3 years of hands-on experience in digital implementation flows. The ideal candidate is highly technical, curious, and eager to drive innovation by combining strong physical design knowledge with modern automation and GenAI-based methodologies. This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII. Key Responsibilities The Engineer will develop, maintain, and improve CAD flows and methodologies for physical design teams, supporting advanced implementation stages from synthesis through place and route, timing closure, power optimization, and signoff readiness. Key responsibilities include: • Develop and support physical design CAD flows using industry-standard EDA tools • Build automation infrastructure for implementation, analysis, reporting, and debug • Support design teams in areas such as synthesis, floorplanning, placement, CTS, routing, timing, power, and physical verification • Create scripts and utilities to improve productivity, quality of results, and flow robustness • Support and enhance flows based on Synopsys Fusion Compiler • Explore and integrate GenAI solutions to accelerate debug, automate repetitive tasks, improve reporting, and enhance engineering productivity • Analyze tool results, logs, QoR metrics, timing reports, congestion, utilization, power, and design-rule issues Basic Qualifications • At least 3 years of experience in Physical Design, CAD, or implementation methodology • Strong understanding of digital physical design concepts, including synthesis, placement, CTS, routing, timing closure, and physical verification • Hands-on experience with Synopsys Fusion Compiler • Experience with scripting languages such as Tcl, Python • Ability to develop automation around EDA tools and large-scale design flows • Good understanding of timing, power, congestion, floorplanning, and QoR analysis • Strong debugging and problem-solving skills • Ability to work closely with multiple engineering teams and support complex design environments • High motivation to learn and apply GenAI technologies in semiconductor design flows. Preferred Experience • Experience with additional tools such as PrimeTime, StarRC, ICC2, Innovus, Voltus, RedHawk, Calibre, or similar • Knowledge of STA, low-power design, UPF, EM/IR, extraction, or signoff flows • Experience building dashboards, regression systems, flow checkers, or automated report analyzers • Familiarity with LLMs, prompt engineering, AI agents, or GenAI-based coding/debug tools • Experience with Git, CI/CD, databases, or cloud-based compute environments We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the world’s most demanding AI and cloud environments. Key Responsibilities • Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip • Collaborate closely with Physical Design team to insure a full power integrity • Partner with Package Design engineers to perform Chip-Package co-analysis (CPM) • Understand root-cause analysis for voltage drop violations and EM risks Basic Qualifications • Bachelor's or Master's degree in Electrical Engineering or a related technical field • 7+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products • Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, or Cadence Voltus) • Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm) • Deep understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture • Deep understanding of EM and trade-offs between signal EM and power grid (PG) EM Preferred Experience • Familiarity with thermal analysis tools and their interaction with electrical performance • Experience working with sign-off criteria and margins for high-volume production chips • Good understanding of timing and P&R • Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution • Ability to write TCL scripts for STA and Fusion Compiler (FC) We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up. If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us. As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the world’s largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale. Key Responsibilities • Execute SoC Top-level physical design and actively drive full-chip convergence • Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff • Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR) • Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon • Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration Basic Qualifications • B.Sc. or M.Sc. in Electrical Engineering • 5+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below) • Proven experience executing complex block or chip-level projects with a proactive, "can-do" approach and excellent communication skills • Deep hands-on expertise in RTL2GDS flows, including P&R, STA, Physical Verification (DRC/LVS), Formal Verification, low-power implementation (UPF/CPF), and EMIR • Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2 or Cadence Innovus) • Practical experience handling both complex macro/subsystem-level designs and Full-Chip integration Preferred Qualifications • Deep understanding of Power & Noise analysis (EM/IR) • Experience with DFT (Design for Test) integration into the physical design flow • Background in high-speed interfaces or data center protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow—you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity. Key Responsibilities • Physical Implementation & Execution • Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards • Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS) • Own macro-level implementation with deep hands-on experience in floorplanning and complex routing • Signoff & Design Integrity • Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR) • Ensure first-pass silicon success through rigorous signoff flows and analysis • Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness • Methodology Development & Cross-Functional Collaboration • Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation • Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity • Leverage scripting and automation to make engineering environment faster and more robust Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 3+ years of hands-on experience in Physical Design at semiconductor companies • Proven expertise in the full RTL2GDS flow with deep hands-on experience in macro-level implementation, floorplanning, and complex routing • Experience working with advanced process technologies (7nm and below) • Solid experience with signoff tools and flows including STA, Logic Equivalence Checking (LEC), DRC, and EMIR analysis • Proficiency in TCL or Python scripting to drive EDA tool flows and automate repetitive tasks Preferred Qualifications • Experience with full-chip level implementation and integration • Knowledge of Power and Noise analysis (SI/PI) to optimize high-performance silicon • Familiarity with Design-for-Test (DFT) requirements and their impact on physical layout • Experience with industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus) • Background in high-speed interface designs or connectivity protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Job Description Silicon One is seeking a CAD Engineer to join the Cisco Silicon One Physical Design team. Meet the Team You'll be part of the Cisco Silicon One team, which is at the heart of Cisco’s software and ASIC design efforts. As part of our team, you’ll contribute to the development of our next-generation network devices—Cisco Silicon One™. Our team operates in a startup-like environment within a stable and leading corporation. Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof. We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of Cisco's future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility. Cisco Silicon One is a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine! Your Impact You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs. Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning. You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS. Minimum Qualifications • A VLSI Design Engineer with extensive experience in backend design • B.Sc./M.Sc. in Electrical Engineering or Computer Engineering with relevant background. • 7+ years of hands-on experience in a relevant domain • Strong understanding of Place & Route flow Preferred Qualifications • Deep understanding of Physical construction and Integration. • Knowledge of Physical Design Verification methods like LVS/DRC and formal verification. • Experience with PD CAD and Physical Design EDA tools (e.g., Synopsys, Cadence). • Ability to support technology adoption and new tool integration. • Great teammate, self-learner, and able to work independently. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Location: Tel-Aviv or Caesarea, Israel, Hybrid Start date: As soon as possible Applications accepted until further notice Who We Are The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. What You'll Do You'll be joining our Physical Design team at Cisco Silicon One, which is at the center of the silicon development at Cisco. Our engineers deal with all chip design aspects: definition, architecture, micro-architecture, design, verification, signoff and validation. We use the latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility. Minimum Qualifications • B.Sc or M.Sc Electrical Engineering or Computer Engineering graduate from leading Israeli Universities. • GPA above 87 (Please attach your grade sheet when applying to expedite the recruitment process). • You are an ambitious and motivated individual, who enjoys big challenges and can quickly ramp on multiple domains. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Job Description Silicon One is seeking a CAD Engineer to join the Cisco Silicon One Physical Design team. Meet the Team You'll be part of the Cisco Silicon One team, which is at the heart of Cisco’s software and ASIC design efforts. As part of our team, you’ll contribute to the development of our next-generation network devices—Cisco Silicon One™. Our team operates in a startup-like environment within a stable and leading corporation. Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof. We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of Cisco's future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility. Cisco Silicon One is a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine! Your Impact You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs. Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning. You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS. Minimum Qualifications • A VLSI Design Engineer with extensive experience in backend design • B.Sc./M.Sc. in Electrical Engineering or Computer Engineering with relevant background. • 2+ years of hands-on experience in a relevant domain • Strong understanding of Place & Route flow Preferred Qualifications • Deep understanding of Physical construction and Integration. • Knowledge of Physical Design Verification methods like LVS/DRC and formal verification. • Experience with PD CAD and Physical Design EDA tools (e.g., Synopsys, Cadence). • Ability to support technology adoption and new tool integration. • Great teammate, self-learner, and able to work independently. #li-as6 Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Cisco Silicon One is seeking a Physical Design Technical Leader. Meet the Team Physical Design team within Cisco Silicon One is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs. We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility. Your Impact You'll be part of the Cisco Silicon One team, which is at the heart of Cisco’s software and ASIC design efforts. You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning. Minimum Requirements • A VLSI Design with extensive experience in backend design • B.Sc./M.Sc. in Electrical Engineering. • Strong understanding of Place & Route flow. • 7+ years of hands-on experience in a relevant domain Preferred/Advantageous Qualifications • Deep understanding of all aspects of Physical construction and Integration. • Knowledge in Physical Design Verification methodology LVS/DRC. • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). • Great teammate, self-learning skills, and ability to work autonomously. #li-as6 Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Cisco Silicon One is seeking a Physical Design Engineer. Meet the Team The Physical Design team within Cisco Silicon One owns backend methodology and flow development from RTL to GDS. The team plays a critical role in developing high-quality VLSI designs for some of Cisco's most advanced silicon products. We work with the latest silicon technologies and processes to build large-scale, complex devices that push the boundaries of feasibility. You will collaborate with experienced engineers across architecture, design, verification, and implementation to deliver high-performance silicon. Your Impact You will be part of the Cisco Silicon One team, which is at the heart of Cisco's software and ASIC design efforts. As a Physical Design Engineer, you will contribute to backend implementation work across key stages of chip design, helping move complex designs from RTL toward GDS. You will work on physical synthesis, place and route, optimization, timing closure, and floor planning activities. Success in this role means delivering high-quality implementation results, learning quickly from senior engineers, and helping improve the flow and methodology used by the team. • Contribute to physical synthesis, place and route, optimization, and timing closure for complex VLSI designs. • Support design floor planning and implementation planning in collaboration with senior physical design engineers. • Analyze timing, congestion, power, area, and design-rule issues and help drive them toward closure. • Work with physical design verification flows, including LVS and DRC, to support clean implementation handoff. • Partner with cross-functional teams to debug implementation issues and improve backend flow quality. Minimum Qualifications: • B.Sc. or M.Sc. in Electrical Engineering or a related field. • 2+ years of hands-on experience in VLSI backend design or a relevant physical design domain. • Strong understanding of the Place & Route flow. • Hands-on experience with physical synthesis, place and route, optimization, timing closure, or design floor planning. Preferred Qualifications: • Understanding of physical construction and integration concepts across backend implementation. • Knowledge of physical design verification methodology, including LVS and DRC. • Familiarity with physical design EDA tools such as Synopsys, Cadence, or similar platforms. • Ability to learn independently, take ownership of assigned tasks, and work effectively with teammates. • Strong problem-solving skills and attention to detail in complex technical environments. #li-as6 Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, automotive, and networking applications. What You Can Expect You will work with both local and global team members on the physical design of complex chips as well as the methodology to enable an efficient and robust design process. This position also provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell. Key responsibilities include: • Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner. • Implement/support designs with multi-voltage designs through all aspects of implementation (place and route, static timing, physical verification) using industry standard EDA tools. • Integrate new AI based design flows • Work with various teams to drive successful design closure. • Provide technical direction, coaching, and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes. • Write scripts in Shell, Python, and TCL to achieve productivity enhancements through AI and automation. What We're Looking For To be successful in this role you must: • Bachelor’s or Master’s, degree in Electrical Engineering, Computer Engineering, or a related field. • 4+ years of progressive experience in back-end physical design and verification. • Good understanding of RTL to GDS flows and methodology. • Expertise in full-chip & sub-hierarchy integration. • Experience integrating and taping out large designs utilizing a digital design environment. • Good scripting skills in Perl, tcl and Python. • Team player with good communication skills • Experience with multi-voltage and low-power design techniques is a plus. • Experience with Cadence Genus and Innovus is preferred. 
This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.
Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-NR1

Our Physical Design group operates in a dynamic, startup-like environment that values deep technical expertise and high-level execution. Each engineer holds end-to-end responsibility - from initial definition and constraints development to execution and full signoff. You will work closely with Design and Architecture teams on RTL modifications and design reviews to ensure seamless convergence. We’re looking for an Experienced Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out. What will your job look like: • Hands-on physical design block owner, leading the process from RTL to GDS. • Lead floorplan exploration in collaboration with Front-End and Architecture teams. • STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis. • Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks. • Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area). All you need is: • BSc or MSc in Computer Engineering or Electrical Engineering. • 5+ years of experience in the Physical Design field • Proficiency in scripting languages (Tcl, Python, Perl, or tcsh). • A team player with excellent communication skills and a “can-do” attitude. Nice to have: • Experience in developing or maintaining implementation tools and design flows. • Experience with high-speed interfaces (DDR/PCIE). • Experience with advanced nodes (5nm and below). Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

Our Physical Design group operates in a dynamic, startup-like environment that values deep technical expertise and high-level execution. Each engineer holds end-to-end responsibility - from initial definition and constraints development to execution and full signoff. You will work closely with Design and Architecture teams on RTL modifications and design reviews to ensure seamless convergence. We’re looking for an Experienced Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out. What will your job look like: • Hands-on physical design block owner from RTL to GDS with horizontal ownership. • Floorplan exploration and collaboration with front-end and architecture teams. • Synthesis exploration and final synthesis including: SDC definition, Scan insertion, Lint, LEC, UPF-LP & Spyglass verification. • Place & Route: from Synthesis to final layout and signoff verification on all tools and floors, with target to achieve best PPA. • STA: timing analysis, working with Sub System and Full Chip owners to manage block and top level constraints for synthesis, P&R and signoff. • Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification. All you need is: • BSc or MSc degree in Computer Engineering or Electrical Engineering. • 8+ years experience in the Physical Design field. • Team player with excellent communication skills, customer orientation, and a “can-do” attitude. • Experience in scripting languages like Tcl/Python/Perl/TCSH. Nice to have: • Experience with high speed interfaces (DDR/PCIE). • Experience with advanced nodes (5nm and below). • Building or maintaining implementation tools and flow. Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

Our Physical Design group operates in a dynamic, startup-like environment that values deep technical expertise and high-level execution. Each engineer holds end-to-end responsibility - from initial definition and constraints development to execution and full signoff. You will work closely with Design and Architecture teams on RTL modifications and design reviews to ensure seamless convergence. We’re looking for an Experienced Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out. What will your job look like: • Hands-on physical design block owner, leading the process from RTL to GDS. • Lead floorplan exploration in collaboration with Front-End and Architecture teams. • STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis. • Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks. • Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area). • Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification. All you need is: • BSc or MSc in Computer Engineering or Electrical Engineering. • 5+ years of experience in the Physical Design field • Proficiency in scripting languages (Tcl, Python, Perl, or tcsh). • A team player with excellent communication skills and a “can-do” attitude. Nice to have: • Experience in developing or maintaining implementation tools and design flows. • Experience with high-speed interfaces (DDR/PCIE). • Experience with advanced nodes (5nm and below). Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

Are you looking to take an active part in shaping next-generation EyeQ SoC technology, driving the process all the way from initial definition to Tape-Out? Our Physical Design group operates in a dynamic, startup-like environment that values deep technical expertise and high-level execution. Each engineer holds end-to-end responsibility - from initial definition and constraints development to execution and full signoff. You will work closely with Design and Architecture teams on RTL modifications and design reviews to ensure seamless convergence. We’re expanding our teams and looking for an Experienced Physical Design Engineer who is ready to make a massive impact NOTE: By applying for this position, you will have the opportunity to indicate your preferred work location: Haifa or Petach Tikva. What will your job look like: • Hands-on physical design block owner, leading the process from RTL to GDS . • Lead floorplan exploration in collaboration with Front-End and Architecture teams. • STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis. • Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks. • Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area). All you need is: • BSc or MSc in Computer Engineering or Electrical Engineering. • 5+ years of experience in the Physical Design field. • Proficiency in scripting languages (Tcl, Python, Perl, or tcsh). • A team player with excellent communication skills and a “can-do” attitude. Nice to have: • Experience in developing or maintaining implementation tools and design flows. • Experience with high-speed interfaces (DDR/PCIE). • Experience with advanced nodes (5nm and below). Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

NVIDIA is looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • You will be developing physical design, STA, Logic eq, Power Integrity flows and methodologies for implementation of networking chips and SOCs. • Work closely with block owners, full Chip STA engineers to assure high quality and timely convergence. • Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips. • Additional responsibilities include participating and developing flow and tool methodologies for timing analysis and closure, power and noise analysis, IR-drop, EM and back-end verification across multiple projects. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience). • 2+ years of fulltime relevant experience in the areas listed below. • Proven experience and strong knowledge in key technical domains, including: Physical Design, STA (Static Timing Analysis) and Timing closure methodologies. • Familiarity with industry-standard tools like PrimeTime (STA) and PrimePower (Power Estimation). • Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role. • Strong sense of ownership, self-learning skills, and ability to work both independently and collaboratively with internal and global teams Ways to stand out from the crowd: • Experience in Signoff domains: STA (PrimeTime), Power Estimation (PrimePower), Power Integrity (RedHawk), Formal eq. (Formality), Backend CAD (Computer-Aided Design), • Knowledge in Tcl/Perl/Python • Versatile • Great teammate NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry! #LI-Hybrid