Physical Design Engineer jobs in Tel Aviv-Yafo

Description For an exciting well-funded start-up, we are looking for a Backend Team member. You will work on complex design, high frequency and low-power budget. Work on ramp-up full RTL2GDSII flow for leading technology and work with external vendors. Requirements Key responsibilities: • RTL-to-GDSII Ownership: execute the complete backend implementation flow (Logic Synthesis, P&R, Tape-Out, IR-drop, etc.), ensuring timely, first-pass silicon success. · Constraints & Timing Closure: Work with design and DFT engineers to write timing and physical constraints, and sign-off on the design using comprehensive Static Timing Analysis (STA), timing eco implementation. · Advanced Physical Implementation: Drive complex physical design tasks including Floorplanning, Power/Ground (PG) Mesh implementation, and handling advanced clocking (CTS/Clock-Mesh) and Hierarchical Design flows. · Low Power Expertise: Define, implement, and verify advanced low power design techniques to meet aggressive power consumption targets. · Design for Manufacturability: Implement and verify Design-for-Test (DFT) strategies and close physical verification challenges, specifically focusing on IR-Drop analysis. · IP Integration & Automation: Execute complex IP integration, incorporating blocks generated by memory compilers and other automated tools. • Collaboration: work closely with design team to understand the data path and correctly implement the floorplan, provide feedback on RTL changes required, Implement logical eco post RTL freeze with design team. • CAD: Improve existing implementation flows to achieve better QOR, write scripts for supporting the P&R flows. Minimum Qualifications • Experience of 10+ years in backend design • Strong expertise of full RTL2GDSII including: • Logic synthesis & equivalence checking • Constraints definition and writing • Complicated IP integration • Memory compilers and other automated block generators • DFT • Floorplanning, PG Mesh • P&R • Low power design including definition, implementation and verification • Timing STA • IR-Drop • BS/MS in EE/CE from lead universities Preferred Qualifications • Team player • Highly motivated • Learning abilities • Good communication • Work with external vendors • Experience in Synopsys/Cadence tools is an advantage • Low power techniques • Clock-mesh/ multi source cts • Hierarchical design flow • Experience in tape-out procedures • RTL code reading A very interesting job and good conditions are guaranteed to the candidates

Description For an exciting well-funded start-up, we are looking for a Backend Team member. You will work on complex design, high frequency and low-power budget. Work on ramp-up full RTL2GDSII flow for leading technology and work with external vendors. Requirements Key responsibilities: • RTL-to-GDSII Ownership: execute the complete backend implementation flow (Logic Synthesis, P&R, Tape-Out, IR-drop, etc.), ensuring timely, first-pass silicon success. · Constraints & Timing Closure: Work with design and DFT engineers to write timing and physical constraints, and sign-off on the design using comprehensive Static Timing Analysis (STA), timing eco implementation. · Advanced Physical Implementation: Drive complex physical design tasks including Floorplanning, Power/Ground (PG) Mesh implementation, and handling advanced clocking (CTS/Clock-Mesh) and Hierarchical Design flows. · Low Power Expertise: Define, implement, and verify advanced low power design techniques to meet aggressive power consumption targets. · Design for Manufacturability: Implement and verify Design-for-Test (DFT) strategies and close physical verification challenges, specifically focusing on IR-Drop analysis. · IP Integration & Automation: Execute complex IP integration, incorporating blocks generated by memory compilers and other automated tools. • Collaboration: work closely with design team to understand the data path and correctly implement the floorplan, provide feedback on RTL changes required, Implement logical eco post RTL freeze with design team. • CAD: Improve existing implementation flows to achieve better QOR, write scripts for supporting the P&R flows. Minimum Qualifications • Experience of 5+ years in backend design • Strong expertise of full RTL2GDSII including: • Logic synthesis & equivalence checking • Constraints definition and writing • Complicated IP integration • Memory compilers and other automated block generators • DFT • Floorplanning, PG Mesh • P&R • Low power design including definition, implementation and verification • Timing STA • IR-Drop • BS/MS in EE/CE from lead universities Preferred Qualifications • Team player • Highly motivated • Learning abilities • Good communication • Work with external vendors • Experience in Synopsys/Cadence tools is an advantage • Low power techniques • Clock-mesh/ multi source cts • Hierarchical design flow • Experience in tape-out procedures • RTL code reading A very interesting job and good conditions are guaranteed to the candidates

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up. If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us. As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the world’s largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale. Key Responsibilities • Execute SoC Top-level physical design and actively drive full-chip convergence • Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff • Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR) • Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon • Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration Basic Qualifications • B.Sc. or M.Sc. in Electrical Engineering • 5+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below) • Proven experience executing complex block or chip-level projects with a proactive, "can-do" approach and excellent communication skills • Deep hands-on expertise in RTL2GDS flows, including P&R, STA, Physical Verification (DRC/LVS), Formal Verification, low-power implementation (UPF/CPF), and EMIR • Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2 or Cadence Innovus) • Practical experience handling both complex macro/subsystem-level designs and Full-Chip integration Preferred Qualifications • Deep understanding of Power & Noise analysis (EM/IR) • Experience with DFT (Design for Test) integration into the physical design flow • Background in high-speed interfaces or data center protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the world’s most demanding AI and cloud environments. Key Responsibilities • Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip • Collaborate closely with Physical Design team to insure a full power integrity • Partner with Package Design engineers to perform Chip-Package co-analysis (CPM) • Understand root-cause analysis for voltage drop violations and EM risks Basic Qualifications • Bachelor's or Master's degree in Electrical Engineering or a related technical field • 7+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products • Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, or Cadence Voltus) • Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm) • Deep understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture • Deep understanding of EM and trade-offs between signal EM and power grid (PG) EM Preferred Experience • Familiarity with thermal analysis tools and their interaction with electrical performance • Experience working with sign-off criteria and margins for high-volume production chips • Good understanding of timing and P&R • Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution • Ability to write TCL scripts for STA and Fusion Compiler (FC) We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity. Key Responsibilities • Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments • Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence • Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments • Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners • Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient Basic Qualifications • B.Sc. in Electrical Engineering or Computer Engineering • 6+ years of hands-on experience in Static Timing Analysis (STA) at semiconductor companies, specifically working on advanced process technologies. (Note: Adjust years of experience based on the exact level you are targeting) • Deep expertise in multi-scenario STA, as well as timing and SDC constraint development and verification at the block and subsystem levels • Solid understanding of advanced margining methodologies, including OCV, AOCV, and POCV, from synthesis through to final sign-off • Solid knowledge of physical design flows (Synthesis, P&R, Physical Verification) and how they intersect with timing closure Preferred Experience • Experience developing and validating constraints using industry-standard tools like Timing Constraints Manager (Synopsys) or TimeVision (Ausdia) • Proven track record of executing STA on complex Macro-level designs and supporting Full-Chip timing integration • Strong background in scripting (Tcl, Python, Perl) and automation to enhance timing closure efficiency We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is a hyper-growth connectivity company building the purpose-built silicon that powers rack-scale AI infrastructure. As a Principal Physical Design Engineer and Team Lead in Israel, you will lead physical design teams that take complex, high-speed mixed-signal and digital SoCs from RTL handoff through tapeout. You will set the technical direction, drive execution across multiple projects, and grow the engineers around you, partnering closely with RTL, DFT, analog, and architecture teams. Your work will directly shape the performance, power, and area of products that connect the world's most demanding AI platforms. Key Responsibilities • Technical Leadership and Team Execution • Lead and mentor physical design engineers, setting priorities, assigning work, and ensuring high-quality, on-time delivery • Drive physical design projects end to end, including planning, scheduling, risk management, and status reporting • Define and evolve physical design methodologies, flows, and best practices across the team • Physical Implementation • Own block-level and top-level implementation: floorplanning, placement, clock tree synthesis, routing, and optimization • Drive timing closure, power integrity, and signal integrity to meet aggressive PPA targets in advanced process nodes • Lead physical verification and sign-off activities, including STA, IR/EM, DRC, LVS, and ECO management • Cross-Functional Collaboration • Partner with RTL design, DFT, analog, and architecture teams to resolve cross-domain implementation challenges early • Work with foundry, EDA vendors, and IP providers to ensure smooth tapeout and silicon bring-up • Contribute to hiring, onboarding, and professional development of team members Basic Qualifications • 10+ years of hands-on experience in physical design of complex SoCs or ASICs • Proven experience leading projects and technical teams through one or more full-chip tapeouts • Deep expertise with industry-standard physical design and sign-off tools (e.g., Cadence Innovus, Synopsys Fusion Compiler/ICC2, PrimeTime, Calibre) • Strong knowledge of timing closure, power/clock distribution, and physical verification in advanced process nodes • Excellent communication skills and the ability to work in a fully in-person, collaborative environment Preferred Qualifications • Experience with high-speed interface designs such as PCIe, Ethernet, or SerDes-based products • Proficiency in scripting languages such as Tcl, Python, or Perl for flow automation • Experience with hierarchical design, low-power methodologies, and ECO-driven closure • Demonstrated ability to mentor engineers and drive continuous improvement in team processes We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Job Description Silicon One is seeking a CAD Engineer to join the Cisco Silicon One Physical Design team. Meet the Team You'll be part of the Cisco Silicon One team, which is at the heart of Cisco’s software and ASIC design efforts. As part of our team, you’ll contribute to the development of our next-generation network devices—Cisco Silicon One™. Our team operates in a startup-like environment within a stable and leading corporation. Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof. We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of Cisco's future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility. Cisco Silicon One is a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine! Your Impact You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs. Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning. You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS. Minimum Qualifications • A VLSI Design Engineer with extensive experience in backend design • B.Sc./M.Sc. in Electrical Engineering or Computer Engineering with relevant background. • 7+ years of hands-on experience in a relevant domain • Strong understanding of Place & Route flow Preferred Qualifications • Deep understanding of Physical construction and Integration. • Knowledge of Physical Design Verification methods like LVS/DRC and formal verification. • Experience with PD CAD and Physical Design EDA tools (e.g., Synopsys, Cadence). • Ability to support technology adoption and new tool integration. • Great teammate, self-learner, and able to work independently. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Job Description Silicon One is seeking a CAD Engineer to join the Cisco Silicon One Physical Design team. Meet the Team You'll be part of the Cisco Silicon One team, which is at the heart of Cisco’s software and ASIC design efforts. As part of our team, you’ll contribute to the development of our next-generation network devices—Cisco Silicon One™. Our team operates in a startup-like environment within a stable and leading corporation. Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof. We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of Cisco's future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility. Cisco Silicon One is a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine! Your Impact You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs. Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning. You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS. Minimum Qualifications • A VLSI Design Engineer with extensive experience in backend design • B.Sc./M.Sc. in Electrical Engineering or Computer Engineering with relevant background. • 2+ years of hands-on experience in a relevant domain • Strong understanding of Place & Route flow Preferred Qualifications • Deep understanding of Physical construction and Integration. • Knowledge of Physical Design Verification methods like LVS/DRC and formal verification. • Experience with PD CAD and Physical Design EDA tools (e.g., Synopsys, Cadence). • Ability to support technology adoption and new tool integration. • Great teammate, self-learner, and able to work independently. #li-as6 Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Cisco Silicon One is seeking a Physical Design Technical Leader. Meet the Team Physical Design team within Cisco Silicon One is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs. We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility. Your Impact You'll be part of the Cisco Silicon One team, which is at the heart of Cisco’s software and ASIC design efforts. You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning. Minimum Requirements • A VLSI Design with extensive experience in backend design • B.Sc./M.Sc. in Electrical Engineering. • Strong understanding of Place & Route flow. • 7+ years of hands-on experience in a relevant domain Preferred/Advantageous Qualifications • Deep understanding of all aspects of Physical construction and Integration. • Knowledge in Physical Design Verification methodology LVS/DRC. • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). • Great teammate, self-learning skills, and ability to work autonomously. #li-as6 Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance. • Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems. • Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification. • Taking part inflows development. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent experience. • 1+ years of relevant experience. • Proven experience in RTL2GDS flows and methodologies. • Knowledge in physical design flows and methodologies (PNR, STA, physical verification). • Deep understanding of all aspects of Physical construction and Integration. • Knowledge in Physical Design Verification methodology LVS/DRC. • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). • Great teammate. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

NVIDIA is looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • You will be in charge of developing physical design, synthesis, STA and Logic eq methodologies for implementation of networking chips and SOCs. • Work closely with block owners. full Chip STA engineers and project managers to assure high quality and timely convergence. • Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips. • Additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience). • At least 2 years of relevant experience • Proficiency using Python, Perl, Tcl, Make scripting. • Expertise in analysing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes. • Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power required and implementing them through ECOs is required. • Knowledge in process variation effect modelling and experience in design convergence taking into account variations. • Successful track record of delivering designs to production is necessary. • Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role. Ways to stand out from the crowd: • Familiarity with synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Innovus/Tempus) • Experience in methodology definition / flow owner of synthesis / Place and Route/ STA steps is an advantage. • Great teammate. • Ownership, self-learning skills, and ability to work autonomously. NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry! #LI-Hybrid

NVIDIA is looking for outstanding STA (Static Timing Analysis) Physical Design Engineers to join our remarkable Networking team in Israel. Our team focuses on building the industry's top high-speed communication devices, providing the highest efficiency and minimal latency. As part of NVIDIA, you'll be working in a meaningful, growing, and highly professional environment where your contributions make a significant impact. If you are ambitious, innovative, and ready to compete on the cutting edge of technology, this is the perfect opportunity for you! What you'll be doing: • Perform advanced Static Timing Analysis (STA) at a chiplet and FC level. • Running Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation. • Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages. • Responsible for a full timing closer and quality approval from pre-layout STA model through signoff. What we need to see: • B.Sc. in Electrical Engineering or Computer Engineering. • 2-3 years of experience as an STA engineer. • Strong ability to quickly adapt to new technology and delve deeply into new areas. • Excellent communication skills and a proven ability to work effectively in a team environment. • Demonstrated drive to develop and implement new solutions. Ways to Stand Out From the Crowd: • Knowledge in physical build flows and methodologies (PNR, STA, physical verification). • Familiarity with Prime Time tool NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

NVIDIA is looking for best-in-class Physical Design Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you will be doing: • Physical design of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance. • Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems. • Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification. • Taking part inflows development. • Act as Partition/Unit level physical design technical leader and focal point. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering. • 5+ years of experience in physical design. • Proven experience in RTL2GDS flows and methodologies. • Knowledge in physical design flows and methodologies (PNR, STA, physical verification). • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). • Great teammate. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance. • Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems. • Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification. • Taking part in flows development. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience. • 5+ years of experience in Physical Design. • Proven experience in RTL2GDS flows and methodologies. • Knowledge in physical design flows and methodologies (PNR, STA, physical verification). • Deep understanding of all aspects of Physical construction and Integration. • Strong background of Physical Design Verification methodology LVS/DRC. • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc). • Great teammate. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

NVIDIA is looking for best-in-class Physical Design Power Engineer to join our outstanding Networking Silicon Power engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput, lowest latency and best Power! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you will be doing: • Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints. • Optimization involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes. • Power estimation and power modeling. What we need to see: • B.SC./ M.SC. or equivalent experience in Electrical Engineering/Computer Engineering. • 1+ years of experience in physical design and/or BE power optimization aspects. • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). • Native ability to leverage modern AI tools to accelerate engineering workflows, productivity, and problem-solving. • Knowledge in physical design flows and methodologies (PNR, STA, physical verification) is an advantage. • FE design experience is an advantage. • Excellent problem-solving, partnership, and interpersonal skills. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance. • Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems. • Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification. • Taking part inflows development. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent experience. • 2+ years of relevant experience. • Proven experience in RTL2GDS flows and methodologies. • Knowledge in physical design flows and methodologies (PNR, STA, physical verification). • Deep understanding of all aspects of Physical construction and Integration. • Knowledge in Physical Design Verification methodology LVS/DRC. • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). • Great teammate. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

NVIDIA is looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • You will be developing physical design, STA, Logic eq, Power Integrity flows and methodologies for implementation of networking chips and SOCs. • Work closely with block owners, full Chip STA engineers to assure high quality and timely convergence. • Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips. • Additional responsibilities include participating and developing flow and tool methodologies for timing analysis and closure, power and noise analysis, IR-drop, EM and back-end verification across multiple projects. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience). • 2+ years of fulltime relevant experience in the areas listed below. • Proven experience and strong knowledge in key technical domains, including: Physical Design, Backend CAD (Computer-Aided Design), STA (Static Timing Analysis) and Timing closure methodologies. • Familiarity with industry-standard tools like PrimeTime (STA) and PrimePower (Power Estimation). • Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role. • Strong sense of ownership, self-learning skills, and ability to work both independently and collaboratively with internal and global teams Ways to stand out from the crowd: • Experience in Signoff domains: STA (PrimeTime), Power Estimation (PrimePower), Power Integrity (RedHawk), Formal eq. (Formality) • Knowledge in Tcl/Perl/Python • Versatile • Great teammate NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry! #LI-Hybrid

NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • You will be in charge of developing full-chip physical design methodologies, Physical Verification development and support through all the projects, Tapeout activities for implementation of networking chips and SOCs. • Work closely with Full Chip Layout owners and block owners, project managers to assure high quality and timely convergence. • Come up with unique and creative solutions to the state of the art FCL physical design problems that are needed for our chips. • We expect you to run, debug, and approve Physical Verification flows across multiple projects, ensuring strict adherence to our high standards. • Participating and developing flow and tool methodologies for fullchip, physical design verification across multiple projects. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience). • You should have at least 5+ years of hands-on Full-chip layout and Physical Verification experience, demonstrating your proven expertise. • A strong background in Physical Verification methodology, including DRC / LVS / ANT / ERC / DFM in advanced process nodes is necessary. • Proficiency using Python, Tcl, Shell, Make scripting. • Experience in Linux environments. • AI tools orientation or alternatively a desire to learn. • Familiarity with physical build EDA tools, including Synopsys (ICC2/FC) and Cadence (Innovus). • Familiarity with Physical Verification tools: Synopsys (ICV), Siemens (Calibre) • Self-motivation, attention to detail, and good interpersonal skills. Ways to stand out from the crowd: • Experience with data collection and analysis • Experience in methodology definition / flow owner of Full-chip / Place and Route • Great teammate. • Ownership, self-learning skills, and ability to work autonomously. NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

NVIDIA is looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • You will be developing physical design, STA, Logic eq, Power Integrity flows and methodologies for implementation of networking chips and SOCs. • Work closely with block owners, full Chip STA engineers to assure high quality and timely convergence. • Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips. • Additional responsibilities include participating and developing flow and tool methodologies for timing analysis and closure, power and noise analysis, IR-drop, EM and back-end verification across multiple projects. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience). • 2+ years of fulltime relevant experience in the areas listed below. • Proven experience and strong knowledge in key technical domains, including: Physical Design, STA (Static Timing Analysis) and Timing closure methodologies. • Familiarity with industry-standard tools like PrimeTime (STA) and PrimePower (Power Estimation). • Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role. • Strong sense of ownership, self-learning skills, and ability to work both independently and collaboratively with internal and global teams Ways to stand out from the crowd: • Experience in Signoff domains: STA (PrimeTime), Power Estimation (PrimePower), Power Integrity (RedHawk), Formal eq. (Formality), Backend CAD (Computer-Aided Design), • Knowledge in Tcl/Perl/Python • Versatile • Great teammate NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry! #LI-Hybrid

NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • Perform physical layout for full-chip level, integration, pinning and bump route • Work with block owners and project managers to assure high quality convergence in all layout aspects • You will be responsible for chip layout from the floorplanning stage through tape-out What we need to see: • An Electronics Engineer certificate or a B.Sc. in Electrical Engineering • You should have 5 years of hands-on Full-chip layout and Physical Verification experience, demonstrating your proven expertise. • A strong background in Physical Verification methodologies, including DRC, LVS, ANT, ERC, and DFM for advanced process nodes, is required • Knowledge in scripts' language: TCL, Unix and Shell • Experience in Linux environments • AI tools orientation or alternatively a desire to learn • Familiarity with physical build EDA tools, including Synopsys (ICC2/FC) and Cadence (Innovus) • Familiarity with Physical Verification tools: Synopsys (ICV), Siemens (Calibre) • Self-motivation, attention to detail and good interpersonal skills Ways to stand out from the crowd: • Experience in methodology definition / flow owner of Full-chip / Place and Route • Great teammate • Ownership, self-learning skills and ability to work autonomously NVIDIA is widely considered to be one of the tech world’s most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you're creative and autonomous, we want to hear from you.