Physical Design Engineer jobs in Haifa

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a Physical Design CAD Engineer with at least 3 years of hands-on experience in digital implementation flows. The ideal candidate is highly technical, curious, and eager to drive innovation by combining strong physical design knowledge with modern automation and GenAI-based methodologies. This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII. Key Responsibilities The Engineer will develop, maintain, and improve CAD flows and methodologies for physical design teams, supporting advanced implementation stages from synthesis through place and route, timing closure, power optimization, and signoff readiness. Key responsibilities include: • Develop and support physical design CAD flows using industry-standard EDA tools • Build automation infrastructure for implementation, analysis, reporting, and debug • Support design teams in areas such as synthesis, floorplanning, placement, CTS, routing, timing, power, and physical verification • Create scripts and utilities to improve productivity, quality of results, and flow robustness • Support and enhance flows based on Synopsys Fusion Compiler • Explore and integrate GenAI solutions to accelerate debug, automate repetitive tasks, improve reporting, and enhance engineering productivity • Analyze tool results, logs, QoR metrics, timing reports, congestion, utilization, power, and design-rule issues Basic Qualifications • At least 3 years of experience in Physical Design, CAD, or implementation methodology • Strong understanding of digital physical design concepts, including synthesis, placement, CTS, routing, timing closure, and physical verification • Hands-on experience with Synopsys Fusion Compiler • Experience with scripting languages such as Tcl, Python • Ability to develop automation around EDA tools and large-scale design flows • Good understanding of timing, power, congestion, floorplanning, and QoR analysis • Strong debugging and problem-solving skills • Ability to work closely with multiple engineering teams and support complex design environments • High motivation to learn and apply GenAI technologies in semiconductor design flows. Preferred Experience • Experience with additional tools such as PrimeTime, StarRC, ICC2, Innovus, Voltus, RedHawk, Calibre, or similar • Knowledge of STA, low-power design, UPF, EM/IR, extraction, or signoff flows • Experience building dashboards, regression systems, flow checkers, or automated report analyzers • Familiarity with LLMs, prompt engineering, AI agents, or GenAI-based coding/debug tools • Experience with Git, CI/CD, databases, or cloud-based compute environments We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow—you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity. Key Responsibilities • Physical Implementation & Execution • Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards • Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS) • Own macro-level implementation with deep hands-on experience in floorplanning and complex routing • Signoff & Design Integrity • Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR) • Ensure first-pass silicon success through rigorous signoff flows and analysis • Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness • Methodology Development & Cross-Functional Collaboration • Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation • Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity • Leverage scripting and automation to make engineering environment faster and more robust Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 3+ years of hands-on experience in Physical Design at semiconductor companies • Proven expertise in the full RTL2GDS flow with deep hands-on experience in macro-level implementation, floorplanning, and complex routing • Experience working with advanced process technologies (7nm and below) • Solid experience with signoff tools and flows including STA, Logic Equivalence Checking (LEC), DRC, and EMIR analysis • Proficiency in TCL or Python scripting to drive EDA tool flows and automate repetitive tasks Preferred Qualifications • Experience with full-chip level implementation and integration • Knowledge of Power and Noise analysis (SI/PI) to optimize high-performance silicon • Familiarity with Design-for-Test (DFT) requirements and their impact on physical layout • Experience with industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus) • Background in high-speed interface designs or connectivity protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Our Physical Design group operates in a dynamic, startup-like environment that values deep technical expertise and high-level execution. Each engineer holds end-to-end responsibility - from initial definition and constraints development to execution and full signoff. You will work closely with Design and Architecture teams on RTL modifications and design reviews to ensure seamless convergence. We’re looking for an Experienced Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out. What will your job look like: • Hands-on physical design block owner from RTL to GDS with horizontal ownership. • Floorplan exploration and collaboration with front-end and architecture teams. • Synthesis exploration and final synthesis including: SDC definition, Scan insertion, Lint, LEC, UPF-LP & Spyglass verification. • Place & Route: from Synthesis to final layout and signoff verification on all tools and floors, with target to achieve best PPA. • STA: timing analysis, working with Sub System and Full Chip owners to manage block and top level constraints for synthesis, P&R and signoff. • Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification. All you need is: • BSc or MSc degree in Computer Engineering or Electrical Engineering. • 8+ years experience in the Physical Design field. • Team player with excellent communication skills, customer orientation, and a “can-do” attitude. • Experience in scripting languages like Tcl/Python/Perl/TCSH. Nice to have: • Experience with high speed interfaces (DDR/PCIE). • Experience with advanced nodes (5nm and below). • Building or maintaining implementation tools and flow. Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

Our Physical Design group operates in a dynamic, startup-like environment that values deep technical expertise and high-level execution. Each engineer holds end-to-end responsibility - from initial definition and constraints development to execution and full signoff. You will work closely with Design and Architecture teams on RTL modifications and design reviews to ensure seamless convergence. We’re looking for an Experienced Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out. What will your job look like: • Hands-on physical design block owner, leading the process from RTL to GDS. • Lead floorplan exploration in collaboration with Front-End and Architecture teams. • STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis. • Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks. • Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area). • Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification. All you need is: • BSc or MSc in Computer Engineering or Electrical Engineering. • 5+ years of experience in the Physical Design field • Proficiency in scripting languages (Tcl, Python, Perl, or tcsh). • A team player with excellent communication skills and a “can-do” attitude. Nice to have: • Experience in developing or maintaining implementation tools and design flows. • Experience with high-speed interfaces (DDR/PCIE). • Experience with advanced nodes (5nm and below). Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

Are you looking to take an active part in shaping next-generation EyeQ SoC technology, driving the process all the way from initial definition to Tape-Out? Our Physical Design group operates in a dynamic, startup-like environment that values deep technical expertise and high-level execution. Each engineer holds end-to-end responsibility - from initial definition and constraints development to execution and full signoff. You will work closely with Design and Architecture teams on RTL modifications and design reviews to ensure seamless convergence. We’re expanding our teams and looking for an Experienced Physical Design Engineer who is ready to make a massive impact NOTE: By applying for this position, you will have the opportunity to indicate your preferred work location: Haifa or Petach Tikva. What will your job look like: • Hands-on physical design block owner, leading the process from RTL to GDS . • Lead floorplan exploration in collaboration with Front-End and Architecture teams. • STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis. • Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks. • Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area). All you need is: • BSc or MSc in Computer Engineering or Electrical Engineering. • 5+ years of experience in the Physical Design field. • Proficiency in scripting languages (Tcl, Python, Perl, or tcsh). • A team player with excellent communication skills and a “can-do” attitude. Nice to have: • Experience in developing or maintaining implementation tools and design flows. • Experience with high-speed interfaces (DDR/PCIE). • Experience with advanced nodes (5nm and below). Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

Job Details: Job Description: Our team is dedicated to optimizing Intel’s cutting-edge process technology to meet the rapidly evolving needs of next-generation silicon designs. Operating at the intersection of process and design development, we drive continuous innovation in both physical design and methodology. We partner closely with Core and SoC design teams worldwide to drive both process and product-level optimization - directly enabling Intel to deliver highly competitive, high-performance and low-power products. Role Overview As a Physical Design & PPA Optimization Engineer, you will play a key role in achieving best-in-class Power, Performance, and Area (PPA) for Intel IPs. You will be responsible for identifying optimization opportunities, developing physical design optimization methodologies, executing the full physical design flow to evaluate PPA landing zones on new Intel process technologies, and translating findings into actionable recommendations that influence strategic decision-making and product direction. Key Responsibilities • Define and implement DTCO experiments to evaluate the interaction between process technology and physical design implementation. • Define and develop design optimization methodologies across all physical design flow domains, such as placement, CTS, routing, and timing closure • Run the full PnR flow to evaluate new technology impacts on PPA metrics. • Identify trade-offs and optimization opportunities at the device, cell, and block Qualifications: Minimum Qualifications • BSc or MSc in Electrical Engineering, Computer Engineering, or a related field • Hands-on experience in physical or circuit design • Basic scripting experience using Python, Tcl, or a similar language • Strong analytical and problem-solving skills • Ability to analyze implementation results and communicate conclusions clearly Preferred Qualifications • 2+ years of experience in physical design or circuit design • Familiarity with physical design implementation flows and methodologies • Solid understanding of transistor, cell, and block-level PPA trade-offs • Experience developing physical design methodologies and analysis tools #LI-DL1 Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Haifa Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *