Astera Labs

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters. As an Senior Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity. Key Responsibilities • Emulation Flow Execution & Implementation • Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging • Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies • Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market • System-Level Debug & Validation • Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs • Ensure rapid cycles from RTL to functional stability through systematic debug approaches • Own technical blocks and drive them to completion independently • Cross-Functional Collaboration • Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios • Ensure seamless hardware-software integration for AI infrastructure connectivity • Collaborate with Design and Verification teams to optimize emulation strategies Basic Qualifications • Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field • 3+ years of hands-on experience in Emulation at semiconductor companies • Deep expertise in emulation flows for large-scale chips using industry-standard emulators (Zebu, Palladium, or Veloce) • Strong background in SystemVerilog for developing, testing, and debugging complex SoC designs • Experience developing and maintaining execution flows for building, running, and debugging emulation models • "Can-do" approach with ability to own technical blocks and drive them to completion independently Preferred Qualifications • Master's degree in Electrical Engineering, Computer Engineering, or related field • Familiarity with EDA tools for Lint, Clock Domain Crossing (CDC), simulation, and synthesis • Proficiency in scripting languages such as Python or TCL for automation and flow enhancement • Experience with standard debug environments (e.g., Verdi) • Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) • Background in hardware-software co-verification methodologies We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. The Role and Its Impact Our firmware team develops the embedded firmware that brings Astera Labs' compute connectivity silicon to life, from boot and initialization through link management, telemetry, error handling, and diagnostics. This firmware runs on the embedded processors inside our chips and ships in data centers powering AI infrastructure around the world. Beyond the firmware, the team also develops the COSMOS SDK, the software layer customers and internal teams use to configure, monitor, update, and debug our devices in their systems. We are looking for an experienced firmware engineer who enjoys working close to the hardware, owns features end to end, and is equally comfortable in a pre-silicon emulation environment and in the lab with real silicon. You understand the whole system, not just the chip: how our devices behave inside customer platforms, and how a customer requirement turns into firmware and SDK. You'll work alongside architects, design and verification engineers, validation teams, and our global firmware teams to take new products from early pre-silicon development through bring-up and into customer deployment. What You'll Be Doing • Having fun! by being part of a very strong and cohesive group. • Design, implement, and maintain real-time embedded firmware in C for high-performance connectivity • Develop low-level drivers, initialization flows, interrupt handling, and control logic for complex hardware blocks • Bring up and debug firmware in pre-silicon environments (emulation) ahead of tape-out, and on silicon after it arrives • Work closely with architecture, design, and verification teams to define HW/FW interfaces and to resolve issues across the hardware/software boundary • Triage and resolve firmware issues reported by validation, product applications, and customers • Take part in design reviews and code reviews, and help improve our firmware quality, tooling, and development practices • Develop and extend the company SDK, including APIs, device management, firmware update, telemetry, and diagnostics capabilities, and keep it aligned with firmware features • Support customer requests and engagements together with product applications and field teams, analyze system-level use cases, and adjust firmware and SDK development to meet customer needs • Collaborate with firmware teams across sites to deliver features on schedule What We're Looking For Required: • BSc/MSc in Computer Science, Electrical Engineering, Computer Engineering, or a related field • 10+ years of hands-on experience as a firmware engineer • Proven experience in embedded and real-time firmware development • Strong programming skills in C on resource-constrained, bare-metal, or RTOS-based systems • Solid understanding of processor architecture, memory-mapped registers, interrupts, and HW/SW interaction • Strong debugging skills on real hardware using JTAG debuggers, logs, and register-level analysis • Broad system-level understanding of how silicon, firmware, SDK, host software, and platform interact, with the ability to turn customer requirements into technical solutions • A team player with excellent communication skills who works well in a collaborative, cross-site environment • Comfort with ambiguity and ownership in a fast-moving, high-growth company Advantage: • Experience with pre-silicon emulation platforms such as Cadence Palladium or Synopsys ZeBu • Knowledge of PCIe (link training, enumeration, configuration space, error handling) • Experience developing SDKs, host-side libraries, or APIs (C/C++ or Python) that interface with embedded firmware • Experience working directly with customers or supporting customer integration and field issues • Experience with silicon bring-up of new SoCs • Python scripting for test automation, debug, or data analysis We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters. As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You won’t just execute tasks; you will define the Formal verification strategy for chips that drive the world’s largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications. Key Responsibilities • Own and develop formal verification environments from scratch through to sign-off • Apply formal verification methodologies and strategies to prove the correctness of intricate designs • Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements • Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs • Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently • Architect and develop generic, common formal functions and properties to be reused across multiple projects Basic Qualifications • Bachelor's degree in Electrical Engineering or a related technical field • 4+ years of hands-on experience in Formal Verification within semiconductor companies • Deep expertise in formal verification methodologies, tools, and flows • Strong understanding of RTL design and verification principles • Experience with industry-standard formal verification tools (Jasper, VC Formal, or similar) • Excellent communication skills, strong analytical thinking, and a proactive, "can-do" approach to problem-solving Preferred Qualifications • Track record of successfully taking complex blocks or subsystems through the entire formal verification lifecycle • Experience with SystemVerilog UVM-based design verification • Knowledge of networking standards (Ethernet, NVLink, UALink, PCIe) • Background in high-speed serial interface verification We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the world’s most demanding AI and cloud environments. Key Responsibilities • Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip • Collaborate closely with Physical Design team to insure a full power integrity • Partner with Package Design engineers to perform Chip-Package co-analysis (CPM) • Understand root-cause analysis for voltage drop violations and EM risks Basic Qualifications • Bachelor's or Master's degree in Electrical Engineering or a related technical field • 7+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products • Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, or Cadence Voltus) • Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm) • Deep understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture • Deep understanding of EM and trade-offs between signal EM and power grid (PG) EM Preferred Experience • Familiarity with thermal analysis tools and their interaction with electrical performance • Experience working with sign-off criteria and margins for high-volume production chips • Good understanding of timing and P&R • Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution • Ability to write TCL scripts for STA and Fusion Compiler (FC) We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects. As a Senior ASIC Design Engineer, you won't just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity. Key Responsibilities • Design Ownership & Implementation • Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support • Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions • Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams • Quality Assurance & Design Optimization • Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient • Apply design techniques to meet PPA (Power, Performance, Area) targets • Contribute to design quality through verification and validation activities • Methodology Innovation & Collaboration • Participate in design methodology improvements and tool automation initiatives • Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter • Collaborate effectively across teams to ensure seamless integration Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 3+ years of experience in logic design at semiconductor companies • Knowledge and experience in Verilog and/or SystemVerilog • Excellent communication skills with ability to work effectively across teams • Understanding of digital design principles and RTL coding best practices Preferred Qualifications • Master's degree in Electrical Engineering or related field • Knowledge of DDR and PCIe protocols and implementation • Understanding of power management techniques for low-power design • Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis • Proficiency in scripting languages such as Python or Perl • Experience with high-speed serial interface designs or connectivity protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up. If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us. As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the world’s largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale. Key Responsibilities • Execute SoC Top-level physical design and actively drive full-chip convergence • Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff • Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR) • Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon • Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration Basic Qualifications • B.Sc. or M.Sc. in Electrical Engineering • 5+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below) • Proven experience executing complex block or chip-level projects with a proactive, "can-do" approach and excellent communication skills • Deep hands-on expertise in RTL2GDS flows, including P&R, STA, Physical Verification (DRC/LVS), Formal Verification, low-power implementation (UPF/CPF), and EMIR • Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2 or Cadence Innovus) • Practical experience handling both complex macro/subsystem-level designs and Full-Chip integration Preferred Qualifications • Deep understanding of Power & Noise analysis (EM/IR) • Experience with DFT (Design for Test) integration into the physical design flow • Background in high-speed interfaces or data center protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow—you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity. Key Responsibilities • Physical Implementation & Execution • Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards • Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS) • Own macro-level implementation with deep hands-on experience in floorplanning and complex routing • Signoff & Design Integrity • Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR) • Ensure first-pass silicon success through rigorous signoff flows and analysis • Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness • Methodology Development & Cross-Functional Collaboration • Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation • Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity • Leverage scripting and automation to make engineering environment faster and more robust Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 3+ years of hands-on experience in Physical Design at semiconductor companies • Proven expertise in the full RTL2GDS flow with deep hands-on experience in macro-level implementation, floorplanning, and complex routing • Experience working with advanced process technologies (7nm and below) • Solid experience with signoff tools and flows including STA, Logic Equivalence Checking (LEC), DRC, and EMIR analysis • Proficiency in TCL or Python scripting to drive EDA tool flows and automate repetitive tasks Preferred Qualifications • Experience with full-chip level implementation and integration • Knowledge of Power and Noise analysis (SI/PI) to optimize high-performance silicon • Familiarity with Design-for-Test (DFT) requirements and their impact on physical layout • Experience with industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus) • Background in high-speed interface designs or connectivity protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Silicon Technical Program Manager to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters. As an Technical Program Manager, you will be the key architect of our silicon’s operational reality. You won’t just track timelines - you will help establish our local execution culture and technical standards, owning the cross-functional journey of transforming complex logic into high-performance silicon. Key Responsibilities • Drive and manage ASIC development and subsystems from concept through to production in collaboration with internal teams and external vendors. • Provide hands-on program management throughout the full development cycle of silicon and firmware, including concept, design, development, fabrication, validation, and production release. • Work closely with the software, hardware, and architecture teams to align with product requirements and ensure all constraints are met. • Lead process improvements across multiple teams and functions to drive better collaboration and efficiency. • Independently manage complex projects with minimal supervision, ensuring timelines and milestones are met. • Deliver high-quality ASIC solutions products while collaborating with product management and architecture teams. Basic Qualifications • Bachelor's degree in Computer Science, Electrical Engineering, or a related technical field • 8+ years of experience in ASIC development and 3+ years in Program or Product Management or Technical/Engineering management • Proven leadership skills, with the ability to manage projects from technical details to the big picture • Experience in managing ASIC design flow, RTL, synthesis, functional verification, and physical layout • Experience in pre-silicon testing (Emulation, FPGA) and post-silicon validation is preferred • Excel in interpersonal communication, relationship building, and collaboration within cross-functional teams • Excellent organizational and leadership skills, and are capable of multitasking in a fast-paced environment Preferred Qualifications • Familiarity with Networking technologies and concepts • Excellent strategic planning and communication skills, with a self-motivated focus on execution We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.