Astera Labs

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. We are looking for a Post-Silicon Validation Engineer with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams. Key Responsibilities • Perform hands-on post-silicon validation • Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability. • Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements. • Drive complex issues from initial failure through root-cause analysis and final resolution. • Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries. • Validate PCIe functionality across different generations, platforms, configurations, and operating conditions. • Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests. • Develop automation to improve validation coverage, debug efficiency, and regression testing. Required Qualifications • BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience. • 5+ years of engineering experience in silicon validation, post-silicon debug, or high-speed interface development. • Strong hands-on knowledge of PCIe architecture and protocol. • Experience working with PCIe analyzers, state traces, registers, logs, eye diagrams, and/or signal-integrity measurements. • Strong problem-solving skills and ability to independently drive issues to root cause. • Experience working across hardware, firmware, and software boundaries. • Good scripting/programming skills, preferably Python • Good Linux knowledge and experience with Linux PCIe debug tools. • Strong communication and collaboration skills. Preferred Qualifications • Experience with PCIe Gen4/Gen5/Gen6/Gen7 • Hands-on experience with PCIe PHY, SerDes, equalization, lane margining, or signal integrity. • Experience with PCIe compliance and interoperability testing. • Experience debugging intermittent, marginal, thermal-sensitive, or corner-case PCIe failures. • Experience with PCIe switches, or networking/accelerator platforms. • Practical experience using AI/ML tools for engineering debug and automation. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Astera Labs is hiring a Manager Design Engineer to help architect and deliver the connectivity silicon powering the world's largest AI clusters. You'll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies. This is a high-impact technical role at a hyper-growth company. You'll partner closely with architecture, verification, DFT, and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap. If you want to ship silicon that defines AI infrastructure, this is the team. Key Responsibilities • RTL Design & Implementation • Own RTL design for assigned blocks from microarchitecture through synthesis sign-off • Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA • Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality • Cross-Functional Execution • Partner with architecture to translate specifications into implementation-ready microarchitecture • Collaborate with verification on testplans, coverage closure, and bug triage • Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure • Technical Leadership & Quality • Mentor junior engineers and contribute to design methodology, scripts, and best practices • Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments • Drive structured, data-driven design decisions in support of aggressive tapeout schedules Basic Qualifications • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field • 5+ years of digital design experience, including at least one full chip from spec to tapeout • Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows • Hands-on experience with timing closure, CDC, lint, and low-power design techniques • Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration Preferred Qualifications • MS or PhD in Electrical Engineering or Computer Engineering • Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs • Familiarity with formal verification, emulation, or assertion-based methodologies • Background in advanced process nodes (7nm, 5nm, or below) • Strong debug skills across pre-silicon and post-silicon environments We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters. As an Expert IC Package Design Lead, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon. You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners.You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling Astera Labs’ products to operate reliably in the world’s most demanding AI and cloud environments. Key Responsibilities • Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing • Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration) • Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices • Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints • Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance • Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets • Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp • Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews Basic Qualifications • 10+ years of hands-on IC BIG package design experience for high-performance semiconductor products, with full ownership from concept through tape-out • Expert proficiency in IC package design tools (Cadence APD / SiP or equivalent) and experience designing complex packages (BGA, FCBGA, FCCSP) • Strong package architecture & integration expertise, including stack-ups, ball/bump maps, constraints, SMT integration, and package BOM ownership • Deep understanding of signal, power, and thermal integrity at the package level, with ability to drive design tradeoffs based on analysis • Proven manufacturing and release experience, including DRC/LVS/DFM, OSAT engagement, and delivering production-ready package designs Preferred Qualifications • Experience with AI, networking, PCIe, CXL, or other high-speed data center interfaces • Familiarity with package reliability standards and qualification (JEDEC, IPC, thermal cycling, HTOL, etc.) • Experience supporting chiplet-based architectures and heterogeneous integration • Prior technical leadership or package ownership on high-volume products We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a Physical Design CAD Engineer with at least 3 years of hands-on experience in digital implementation flows. The ideal candidate is highly technical, curious, and eager to drive innovation by combining strong physical design knowledge with modern automation and GenAI-based methodologies. This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII. Key Responsibilities The Engineer will develop, maintain, and improve CAD flows and methodologies for physical design teams, supporting advanced implementation stages from synthesis through place and route, timing closure, power optimization, and signoff readiness. Key responsibilities include: • Develop and support physical design CAD flows using industry-standard EDA tools • Build automation infrastructure for implementation, analysis, reporting, and debug • Support design teams in areas such as synthesis, floorplanning, placement, CTS, routing, timing, power, and physical verification • Create scripts and utilities to improve productivity, quality of results, and flow robustness • Support and enhance flows based on Synopsys Fusion Compiler • Explore and integrate GenAI solutions to accelerate debug, automate repetitive tasks, improve reporting, and enhance engineering productivity • Analyze tool results, logs, QoR metrics, timing reports, congestion, utilization, power, and design-rule issues Basic Qualifications • At least 3 years of experience in Physical Design, CAD, or implementation methodology • Strong understanding of digital physical design concepts, including synthesis, placement, CTS, routing, timing closure, and physical verification • Hands-on experience with Synopsys Fusion Compiler • Experience with scripting languages such as Tcl, Python • Ability to develop automation around EDA tools and large-scale design flows • Good understanding of timing, power, congestion, floorplanning, and QoR analysis • Strong debugging and problem-solving skills • Ability to work closely with multiple engineering teams and support complex design environments • High motivation to learn and apply GenAI technologies in semiconductor design flows. Preferred Experience • Experience with additional tools such as PrimeTime, StarRC, ICC2, Innovus, Voltus, RedHawk, Calibre, or similar • Knowledge of STA, low-power design, UPF, EM/IR, extraction, or signoff flows • Experience building dashboards, regression systems, flow checkers, or automated report analyzers • Familiarity with LLMs, prompt engineering, AI agents, or GenAI-based coding/debug tools • Experience with Git, CI/CD, databases, or cloud-based compute environments We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. We are seeking an experienced Principal Architect to lead the architecture of high-performance connectivity solutions, with a strong focus on PCIe, high-speed networking, and Ethernet-based systems. This role will define next-generation architectures for AI infrastructure, working at the intersection of silicon, system, and protocol design. You will play a key role in shaping innovative solutions that enable hyperscale customers to build scalable, high-bandwidth, and low-latency systems. This is a unique opportunity to join a new and growing Israel site, influence technical direction, and take ownership of critical architectural decisions impacting industry-leading products. Key Responsibilities • Define and drive system and chip-level architecture for high-speed connectivity products • Lead architecture for PCIe-based interconnects, networking protocols, and Ethernet subsystems • Analyze system requirements and translate them into scalable and efficient hardware architectures • Drive tradeoff analysis across performance, power, latency, area, and cost • Collaborate with cross-functional teams including RTL, Physical Design, Firmware, Validation, and Product Engineering • Define and review micro-architecture specifications and ensure alignment across teams • Contribute to standard-based and custom protocols for next-generation AI infrastructure • Support performance modeling, simulation, and architectural validation • Work closely with customers and partners to understand emerging use cases and requirements • Mentor engineers and help build strong technical leadership within the Israel R&D center Basic Qualifications • 10+ years of experience in semiconductor architecture, ASIC design, or system engineering • Strong expertise in PCIe architecture (Gen4/5/6+) and its ecosystem • Deep understanding of Networking and Ethernet (e.g., 25G/50G/100G/400G and beyond) • Experience designing high-speed, low-latency data paths • Solid understanding of SoC architecture and integration challenges • Experience working across full chip development lifecycle • Strong analytical and problem-solving skills with ability to evaluate complex tradeoffs • Ability to influence and collaborate across multiple engineering domains Preferred Experience • Experience with CXL, NVLink, UALink, or other advanced interconnect protocols • Background in AI/ML infrastructure, data center systems, or hyperscaler environments • Experience with SerDes-based systems and high-speed PHY integration • Familiarity with networking stacks, switching, or RDMA technologies • Experience with performance modeling tools and architectural simulators • Knowledge of power/performance optimization techniques at system level • Track record of driving architecture from concept to silicon We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Principal DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters. As a Principal DFT Engineer, you will provide technical leadership across the full DFT lifecycle—from architecture and specification through implementation, verification, and silicon bring-up. You will define and drive DFT strategy, establish robust methodologies, and lead execution to ensure high test quality and manufacturability. This role requires deep expertise, cross-functional influence, and the ability to drive DFT excellence across projects and teams. This is a critical leadership position with high impact on first-pass silicon success and production quality for next-generation AI connectivity solutions. Key Responsibilities DFT Architecture & Technical Leadership • Define and own DFT architecture for complex SoCs, including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG strategies • Lead DFT planning, specification, and quality tracking across the project lifecycle • Provide technical leadership and drive DFT sign-off readiness to ensure successful tapeout Execution Across the Full Lifecycle • Lead DFT implementation, integration, and verification at block, full-chip and chiplet levels • Own end-to-end DFT activities from specification through silicon bring-up and production support • Ensure high test coverage, robust pattern generation, and alignment with manufacturing requirements Methodology & Cross-Functional Impact • Develop and drive scalable DFT methodologies, flows, and automation frameworks • Collaborate closely with RTL, Physical Design, STA, and Test Engineering teams to ensure design-for-test readiness • Optimize DFT integration across front-end and backend flows to improve quality, PPA, and turnaround time Basic Qualifications • Bachelor’s degree in Electrical Engineering or related technical field (Master’s preferred) • 12+ years of experience in DFT design, implementation, and verification for complex ASIC/SoC designs • Proven experience in leading DFT activities across full chip development cycles • Deep expertise in DFT techniques including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG • Strong understanding of DFT and Physical Design flows, including timing implications and integration challenges • Experience with industry-standard DFT tools (Siemens Tessent, Synopsys TestMAX or equivalent) • Solid experience with DFT verification methodologies and coverage analysis • Strong scripting skills (Tcl, Python, or Perl) for automation and flow development Preferred Qualifications • Experience with advanced process nodes (7nm and below) • Background in high-speed connectivity designs (PCIe, Ethernet, CXL, or similar) • Experience with hierarchical DFT methodologies and large multi-die or chiplet-based systems • Knowledge of silicon bring-up, production test flows, and yield optimization • Familiarity with STA, low-power design, and CDC as it relates to DFT integration • Strong leadership and communication skills, with ability to influence cross-functional teams globally We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters. As a DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools—you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity. Key Responsibilities • DFT Architecture & Strategy • Be part of the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support • Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards • Design and implement DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG for high-end devices • Test Pattern Development & Optimization • Generate and optimize high-quality test and debug patterns for production • Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance • Drive test coverage and quality metrics to meet stringent manufacturing requirements • Cross-Functional Collaboration & Methodology Innovation • Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR • Participate in developing and maintaining cutting-edge DFT implementation flows • Automate and improve methodologies using advanced scripting and tools Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 4+ years of hands-on experience in DFT roles at semiconductor companies • Experience in DFT flows and architectures including JTAG/iJTAG, MBIST, Scan, and ATPG • Good understanding of logic design, verification, debug, and Static Timing Analysis (STA) • Scripting proficiency in Tcl, Perl, Python, or Shell for automation and innovation Preferred Qualifications • Master's degree in Electrical Engineering or related field • Experience with industry-standard EDA tools from Synopsys (TestMAX) or Siemens (Tessent) • Experience in chip bring-up and mass production activities • Background in advanced process technologies (7nm and below) • Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) and their specific test requirements • Excellent communication skills with ability to work effectively in global team environments We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. The Role and Its Impact Our firmware team develops the embedded firmware that brings Astera Labs' compute connectivity silicon to life, from boot and initialization through link management, telemetry, error handling, and diagnostics. This firmware runs on the embedded processors inside our chips and ships in data centers powering AI infrastructure around the world. Beyond the firmware, the team also develops the COSMOS SDK, the software layer customers and internal teams use to configure, monitor, update, and debug our devices in their systems. We are looking for an experienced firmware engineer and PCIe expert who enjoys working close to the hardware, owns features end to end, and has a proven track record of developing and debugging firmware both pre-silicon and post-silicon. You know PCIe in depth, from link training and enumeration to error handling and recovery, and you're the person others turn to when a PCIe link or device misbehaves. You understand the whole system, not just the chip: how our devices behave inside customer platforms, and how a customer requirement turns into firmware and SDK. You'll work alongside architects, design and verification engineers, validation teams, and our global firmware teams to take new products from early pre-silicon development through bring-up and into customer deployment. What You'll Be Doing • Having fun! by being part of a very strong and cohesive group. • Design and develop real-time embedded firmware in C, including low-level drivers and control logic for complex hardware blocks • Own PCIe firmware features end to end: link training, enumeration, error handling, and recovery • Develop and debug firmware pre-silicon (emulation) and lead post-silicon bring-up and debug in the lab • Debug complex PCIe and system-level issues with architecture, design, validation, and customer teams • Develop and extend the company SDK in step with firmware features • Support customer requests and adjust firmware and SDK development to meet their needs What We're Looking For Required: • BSc/MSc in Computer Science, Electrical Engineering, Computer Engineering, or a related field • 10+ years of hands-on experience as a firmware engineer • Proven experience in embedded and real-time firmware development • Strong programming skills in C on resource-constrained, bare-metal, or RTOS-based systems • Solid understanding of processor architecture, memory-mapped registers, interrupts, and HW/SW interaction • Expert-level knowledge of PCIe: LTSSM and link training, enumeration, configuration space, error handling (AER), and reset and recovery flows • Experience with PCIe protocol analyzers and exercisers (e.g., Teledyne LeCroy, Keysight) • Proven hands-on experience in both pre-silicon and post-silicon firmware development and debugging, including silicon bring-up of new SoCs • Strong debugging skills on real hardware using JTAG debuggers, logs, and register-level analysis • Broad system-level understanding of how silicon, firmware, SDK, host software, and platform interact, with the ability to turn customer requirements into technical solutions • A team player with excellent communication skills who works well in a collaborative, cross-site environment • Comfort with ambiguity and ownership in a fast-moving, high-growth company Location This position is based in our Tel Aviv, Israel office. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Principal Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters. As an Principal Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity. Key Responsibilities • Emulation Flow Execution & Implementation • Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging • Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies • Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market • System-Level Debug & Validation • Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs • Ensure rapid cycles from RTL to functional stability through systematic debug approaches • Own technical blocks and drive them to completion independently • Cross-Functional Collaboration • Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios • Ensure seamless hardware-software integration for AI infrastructure connectivity • Collaborate with Design and Verification teams to optimize emulation strategies Basic Qualifications • Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field • 10+ years of hands-on experience in Emulation at semiconductor companies • Deep expertise in emulation flows for large-scale chips using industry-standard emulators (Zebu, Palladium, or Veloce) • Strong background in SystemVerilog for developing, testing, and debugging complex SoC designs • Experience developing and maintaining execution flows for building, running, and debugging emulation models • "Can-do" approach with ability to own technical blocks and drive them to completion independently Preferred Qualifications • Master's degree in Electrical Engineering, Computer Engineering, or related field • Familiarity with EDA tools for Lint, Clock Domain Crossing (CDC), simulation, and synthesis • Proficiency in scripting languages such as Python or TCL for automation and flow enhancement • Experience with standard debug environments (e.g., Verdi) • Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) • Background in hardware-software co-verification methodologies We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we are seeking a motivated Physical Design Student to join our founding local engineering team. This is a unique opportunity to kickstart your career in the semiconductor industry. Working alongside senior industry veterans, you will gain hands-on experience in backend execution and advanced methodologies for cutting-edge chips that power the world's largest AI clusters. If you are passionate about silicon hardware, eager to learn, and thrive on solving complex engineering challenges, this role offers the perfect bridge between your academic studies and a high-impact career. Key Responsibilities Guided Implementation & Learning • Partner with and learn from senior engineers to support the physical implementation journey, including synthesis, floorplanning, Place & Route (P&R), and Clock-Tree Synthesis (CTS) • Assist in macro-level implementation and develop hands-on skills in complex layout routing • Participate in deep-submicron process challenges under close professional mentorship Signoff & Design Integrity Support • Assist in running engineering checks for design integrity, including Static Timing Analysis (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR) • Learn to apply Logic Equivalence Checking (LEC) to help guarantee design correctness • Gain exposure to the rigorous flows required to ensure first-pass silicon success Scripting & Cross-Functional Collaboration • Leverage and develop scripting tools to automate repetitive tasks and optimize the engineering environment • Collaborate with Architecture, Design, and DFT teams to understand how different chip design disciplines intersect • Actively participate in team reviews and technical discussions to ramp up backend methodologies Basic Qualifications • Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field • Strong academic foundation in digital systems, VLSI design, or semiconductor devices. • Familiarity with Python, TCL, Bash, or Perl. • Ability to work at least 2 days per week at our Haifa/Tel Aviv Center • A "can-do" attitude with a passion for solving complex technical challenges • Fluent in Hebrew and English with the ability to work effectively in a team environment Preferred Qualifications • Prior experience from a previous VLSI/Hardware student position or a significant academic project in physical design/VLSI • Hands-on university lab experience with industry-standard EDA tools (e.g., Synopsys Fusion Compiler/ICC2, Cadence Innovus) • Understanding of basic verification concepts (STA, DRC, LVS) • Fast learner with a proactive attitude and a passion for deep-tech hardware infrastructure We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is a hyper-growth connectivity company building the purpose-built silicon that powers rack-scale AI infrastructure. As a Principal Physical Design Engineer and Team Lead in Israel, you will lead physical design teams that take complex, high-speed mixed-signal and digital SoCs from RTL handoff through tapeout. You will set the technical direction, drive execution across multiple projects, and grow the engineers around you, partnering closely with RTL, DFT, analog, and architecture teams. Your work will directly shape the performance, power, and area of products that connect the world's most demanding AI platforms. Key Responsibilities • Technical Leadership and Team Execution • Lead and mentor physical design engineers, setting priorities, assigning work, and ensuring high-quality, on-time delivery • Drive physical design projects end to end, including planning, scheduling, risk management, and status reporting • Define and evolve physical design methodologies, flows, and best practices across the team • Physical Implementation • Own block-level and top-level implementation: floorplanning, placement, clock tree synthesis, routing, and optimization • Drive timing closure, power integrity, and signal integrity to meet aggressive PPA targets in advanced process nodes • Lead physical verification and sign-off activities, including STA, IR/EM, DRC, LVS, and ECO management • Cross-Functional Collaboration • Partner with RTL design, DFT, analog, and architecture teams to resolve cross-domain implementation challenges early • Work with foundry, EDA vendors, and IP providers to ensure smooth tapeout and silicon bring-up • Contribute to hiring, onboarding, and professional development of team members Basic Qualifications • 10+ years of hands-on experience in physical design of complex SoCs or ASICs • Proven experience leading projects and technical teams through one or more full-chip tapeouts • Deep expertise with industry-standard physical design and sign-off tools (e.g., Cadence Innovus, Synopsys Fusion Compiler/ICC2, PrimeTime, Calibre) • Strong knowledge of timing closure, power/clock distribution, and physical verification in advanced process nodes • Excellent communication skills and the ability to work in a fully in-person, collaborative environment Preferred Qualifications • Experience with high-speed interface designs such as PCIe, Ethernet, or SerDes-based products • Proficiency in scripting languages such as Tcl, Python, or Perl for flow automation • Experience with hierarchical design, low-power methodologies, and ECO-driven closure • Demonstrated ability to mentor engineers and drive continuous improvement in team processes We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Package Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, Driving the physical implementation strategy for chips that power the world's largest AI clusters. As a Package Design Engineer, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon. You will execute the package flow, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners. You will be responsible for implementing package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling Astera Labs’ products to operate reliably in the world’s most demanding AI and cloud environments. Key Responsibilities • Execute end-to-end IC package design, from early feasibility and detailed design through to qualification and high-volume manufacturing • Implement package architecture and utilize advanced technologies (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration) • Drive signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices • Perform package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and apply mechanical constraints • Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance • Interface directly with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets are met • Conduct package-related risk assessments, failure analysis, and corrective actions during bring-up and production ramp • Support NPI, qualification, and product sustainment activities, including vendor technical reviews Basic Qualifications • 5+ years of hands-on IC package design experience for high-performance semiconductor products, with full technical ownership from concept through tape-out • Expert proficiency in IC package design tools (Cadence APD / SiP or equivalent) and hands-on experience designing complex packages (BGA, FCBGA, FCCSP) • Strong package integration expertise, including stack-ups, ball/bump maps, constraints, SMT integration, and package BOM ownership • Deep understanding of signal, power, and thermal integrity at the package level, with the ability to execute design tradeoffs based on analysis • Proven manufacturing and release experience, including running DRC/LVS/DFM, OSAT engagement, and delivering production-ready package designs Preferred Qualifications • Experience with AI, networking, PCIe, CXL, or other high-speed data center interfaces • Familiarity with package reliability standards and qualification (JEDEC, IPC, thermal cycling, HTOL, etc.) • Experience supporting chiplet-based architectures and heterogeneous integration • Demonstrated track record of complete technical package ownership on high-volume products We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Staff / Principal ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects. As a Staff / Principal ASIC Design Engineer, you won't just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity. Key Responsibilities • Design Ownership & Implementation • Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support • Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions • Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams • Quality Assurance & Design Optimization • Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient • Apply design techniques to meet PPA (Power, Performance, Area) targets • Contribute to design quality through verification and validation activities • Methodology Innovation & Collaboration • Participate in design methodology improvements and tool automation initiatives • Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter • Collaborate effectively across teams to ensure seamless integration Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 5+ years of experience in logic design at semiconductor companies • Knowledge and experience in Verilog and/or SystemVerilog • Excellent communication skills with ability to work effectively across teams • Understanding of digital design principles and RTL coding best practices Preferred Qualifications • Master's degree in Electrical Engineering or related field • Knowledge of DDR and PCIe protocols and implementation • Understanding of power management techniques for low-power design • Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis • Proficiency in scripting languages such as Python or Perl • Experience with high-speed serial interface designs or connectivity protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Astera Labs is seeking a dynamic and technical Manager, System Validation Engineering to lead our post-silicon and system validation teams in Haifa. In this leadership role, you will direct engineering teams responsible for validating high-performance PCIe and connectivity fabric switch products built for rack-scale AI and cloud data centers. You will combine hands-on technical oversight with strong people management, guiding engineers through validation strategy, automated test execution, deep root-cause investigations, and direct customer integration support. This is a critical leadership position to shape our validation methodologies, scale automation infrastructure, and ensure the flawless execution and launch of purpose-built connectivity silicon. Success Looks Like • Execution & On-Time Delivery: New silicon, platforms, and AI fabric switch solutions are brought up and certified on schedule with rigorous, reproducible validation results. • Team Leadership & Scale: Engineering talent is mentored, engaged, and effectively deployed across multiple projects, fostering a culture of technical excellence, accountability, and innovation. • Automation & Efficiency: Test suites and infrastructure are scaled to maximize test coverage, minimize manual effort, and drive down test cycle times. • Customer Trust & Resolution: Complex cross-functional system issues are resolved rapidly through data-backed root-cause analysis, resulting in high customer satisfaction during integration and deployment. Key Responsibilities Leadership & Team Management • Lead, mentor, and grow a team of high-performing System Validation Engineers at Haifa • Drive resource planning, project scheduling, engineer capacity tracking, and milestone execution across multiple complex silicon programs. • Foster strong cross-functional alignment with Silicon Design, Firmware, Software, Hardware, Product, and Applications teams. • Attract, hire, and develop top engineering talent while championing technical growth and career development. Validation Strategy & Planning • Oversee the creation of comprehensive validation plans for AI fabric switch products covering functionality, performance, reliability, stress, and interoperability. • Translate complex customer and system requirements into measurable test objectives, coverage goals, and product certification criteria. • Establish clear, data-driven reporting metrics, status dashboards, and specification-compliance assessments for executive leadership and key customers. • Guide technical execution for silicon and platform bring-up activities, verifying boot and runtime behavior on x86 and ARM systems. • Oversee complex debugging across PCIe, NVMe, Ethernet, firmware, hardware, and system layers using advanced lab equipment and CPU-based tool suites. • Drive systematic root-cause problem solving, guiding engineers through structured experiment design to isolate and resolve complex silicon, firmware, and board-level issues. • Scale validation infrastructure supporting test orchestration, advanced data collection, statistical analysis, and automated report generation. • Continually optimize validation workflows and lab debug tools to accelerate issue resolution and improve regression coverage. Basic Qualifications • Bachelor’s degree in Electrical Engineering, Computer Science • 8+ years of total experience in silicon product development, post-silicon validation, or system engineering for server, storage, networking, or AI infrastructure applications, including 4+ years of technical leadership or people management experience. • Demonstrated experience leading engineering teams, managing project schedules, and driving execution in a fast-paced environment. • Proven track record with complex silicon and system bring-up, validation, and laboratory debug methodologies. • Strong Python automation background for test orchestration, bench control, and data analysis. • Exceptional communication, stakeholder management, and cross-functional leadership skills. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Staff/ Principal Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly. As a Staff/ Principal Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity. Key Responsibilities • Verification Environment Development • Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks • Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing • Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified • Coverage & Quality Assurance • Implement functional coverage models and analyze results to identify gaps in the verification process • Drive designs toward 100% verification closure through comprehensive test development • Contribute to verification methodology improvements and best practices • Debug & Cross-Functional Collaboration • Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle • Apply analytical skills and debugging techniques to solve intricate verification challenges • Collaborate effectively in a fast-paced, team-oriented R&D environment Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 5+ years of proven experience in ASIC verification within the semiconductor industry • Hands-on experience developing components within complex verification environments using SystemVerilog • Strong working knowledge of standard verification methodologies, specifically UVM • Sharp analytical mind with passion for debugging and technical problem-solving • Excellent communication skills with ability to thrive in collaborative R&D environments Preferred Qualifications • Master's degree in Electrical Engineering or related field • Familiarity with Formal Verification or Emulation flows • Basic proficiency in scripting languages such as Python or Tcl to automate verification tasks • Exposure to industry-standard protocols such as AMBA, PCIe, Ethernet, or CXL • Experience with assertion-based verification and constrained-random testing • Background in connectivity or networking silicon verification We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Staff DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters. As a Staff DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools—you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity. Key Responsibilities • DFT Architecture & Strategy • Own the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support • Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards • ​DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG methodologies • Test Pattern Development & Optimization • Generate and optimize high-quality test and debug patterns for production • Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance • Drive test coverage and quality metrics to meet stringent manufacturing requirements • Cross-Functional Collaboration & Methodology Innovation • Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR • Participate in developing and maintaining cutting-edge DFT implementation flows • Automate and improve methodologies using advanced scripting and tools Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 8+ years of hands-on experience in DFT roles at semiconductor companies • Deep expertise in DFT flows and architectures including JTAG/iJTAG, MBIST, Scan, and ATPG • Proficiency with industry-standard EDA tools from Synopsys (TestMAX) or Mentor (Tessent) • Strong understanding of logic design, verification, debug, and Static Timing Analysis (STA) • Scripting proficiency in Tcl, Perl, Python, or Shell for automation and innovation Preferred Qualifications • Master's degree in Electrical Engineering or related field • Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) and their specific test requirements • Experience in chip bring-up and mass production activities • Background in advanced process technologies (7nm and below) • Excellent communication skills with ability to work effectively in global team environments We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary System Validation Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters. Job Description The mission of this role is to perform system validation for Astera Lab’s highly advanced devices, that includes defining strategy, develop tools, innovate, be creative to make sure devices are performing as they should in all aspects, logical, performance, durability, stress and more. You will be part of the site located at Israel (Haifa – Matam), surrounded with highly experienced and professional engineers who will escort, mentor and support you on your journey at Astera Labs Israel. Basic qualifications • Strong academic and technical background in electrical or computer engineering • 3-5 years experience validating and/or developing complex SoC/silicon products for Networking and/or Server & Storage applications • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and work with minimal guidance and supervision. • Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind! Required experience. • Hands-on, thorough knowledge of high-speed protocols like Ethernet CXL, PCIe, NVMe,. • Silicon/System bring-up, validation, and debug experience, including customer’s systems. • A Python coding experience • Familiarity with validation techniques C, C++ • Experience with lab equipment as protocol analyzers, chambers, in-circuit debuggers, and CPU-based tool suites. • Familiarity with lab testing automation techniques Preferred experience • Familiarity with devices trees and related debugging techniques. • Familiarity with board system design • C\C++ for embedded FW and device drivers • Basic understanding of x86/ARM architecture, UEFI/Linux boot sequence • Familiarity with CXL compliance standards and ability to follow and be involved in compliance consortiums to adapt the tests to be run from X86/ARM based platforms. • Experience working with DRAM memory vendors on DDR4 or DDR5 to identify issues and working on SoC HW/FW to improve memory calibration and tuning sequences. • Knowledge of memory subsystem compliance from a data integrity and RAS is a plus. • Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc. Astera Labs is a young light-footed company, allowing our engineers to fully exploit their creativity and innovative thinking to enable you to grow up your engineering capabilities to the maximum! We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity. Key Responsibilities • Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments • Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence • Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments • Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners • Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient Basic Qualifications • B.Sc. in Electrical Engineering or Computer Engineering • 6+ years of hands-on experience in Static Timing Analysis (STA) at semiconductor companies, specifically working on advanced process technologies. (Note: Adjust years of experience based on the exact level you are targeting) • Deep expertise in multi-scenario STA, as well as timing and SDC constraint development and verification at the block and subsystem levels • Solid understanding of advanced margining methodologies, including OCV, AOCV, and POCV, from synthesis through to final sign-off • Solid knowledge of physical design flows (Synthesis, P&R, Physical Verification) and how they intersect with timing closure Preferred Experience • Experience developing and validating constraints using industry-standard tools like Timing Constraints Manager (Synopsys) or TimeVision (Ausdia) • Proven track record of executing STA on complex Macro-level designs and supporting Full-Chip timing integration • Strong background in scripting (Tcl, Python, Perl) and automation to enhance timing closure efficiency We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly. As a Senior Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity. Key Responsibilities • Verification Environment Development • Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks • Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing • Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified • Coverage & Quality Assurance • Implement functional coverage models and analyze results to identify gaps in the verification process • Drive designs toward 100% verification closure through comprehensive test development • Contribute to verification methodology improvements and best practices • Debug & Cross-Functional Collaboration • Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle • Apply analytical skills and debugging techniques to solve intricate verification challenges • Collaborate effectively in a fast-paced, team-oriented R&D environment Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 3+ years of proven experience in ASIC verification within the semiconductor industry • Hands-on experience developing components within complex verification environments using SystemVerilog • Strong working knowledge of standard verification methodologies, specifically UVM • Sharp analytical mind with passion for debugging and technical problem-solving • Excellent communication skills with ability to thrive in collaborative R&D environments Preferred Qualifications • Master's degree in Electrical Engineering or related field • Familiarity with Formal Verification or Emulation flows • Basic proficiency in scripting languages such as Python or Tcl to automate verification tasks • Exposure to industry-standard protocols such as AMBA, PCIe, Ethernet, or CXL • Experience with assertion-based verification and constrained-random testing • Background in connectivity or networking silicon verification We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Senior System Validation Engineer Astera Labs is seeking a motivated Senior System Validation Engineer to join our growing post-silicon validation team in Israel and support next-generation connectivity products for AI and data-center applications. In this role, you will perform system-level post-silicon validation, characterization, and debug across silicon, hardware, firmware, and software. You will support silicon bring-up and PVT/corner testing, develop and execute functional and system validation tests, analyze results, and work with cross-functional teams to identify and resolve complex system issues. This is a highly hands-on lab position. The primary location is Haifa, with temporary support at the Ramat Gan lab as needed. Key Responsibilities: • Develop and execute post-silicon functional and system validation from silicon bring-up through production readiness. • Run PVT, silicon corner, stress, characterization, and qualification testing across a wide range of operating conditions. • Develop validation tests to verify functionality, performance, stability, power, and operating margins. • Debug issues across silicon, hardware, firmware, drivers, and system software. • Validate high-speed interfaces such as PCIe, CXL, Ethernet/SerDes, and DDR, as well as common system interfaces. • Develop Python scripts and automation to improve validation coverage, regression, and test efficiency. • Analyze validation data, identify issues and trends, and drive problems to root cause and closure. • Work closely with hardware, architecture, firmware, software, design, and DV teams to investigate and resolve issues. • Support the transition of new silicon from initial bring-up to a qualified, production-ready product. • Operate system platforms and laboratory equipment to support validation and debug. • Document test results, issues, root cause, and recommendations and communicate findings clearly. Basic Qualifications: • B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, Computer Science, or a related field. • 6+ years of experience in post-silicon, system, hardware, or product validation. • Hands-on experience with SoC/silicon bring-up, functional validation, and system-level debug. • Experience developing and executing validation plans, test cases, and characterization experiments. • Strong Python scripting and test automation skills. • Strong hardware debugging, analytical, and problem-solving skills with the ability to work independently. • Experience debugging issues across hardware, firmware, and software. • Experience validating high-speed interfaces such as PCIe, Ethernet, SerDes, CXL, or DDR. • Hands-on experience working in a hardware or system validation laboratory. • Strong communication and cross-functional collaboration skills. Preferred Qualifications: • Experience with PVT validation, silicon corner testing, characterization, qualification, and margin analysis. • Experience with server, storage, networking, or AI infrastructure products. • Familiarity with PCIe/CXL architecture and high-speed SerDes technologies. • Experience with oscilloscopes, BERTs, protocol analyzers, traffic generators, or similar lab equipment. • Working knowledge of Python, firmware, Linux, and system-level software debugging. • Experience developing automated validation and regression environments. • Familiarity with Git and software development practices. • Experience with pre-silicon validation, emulation, or hardware prototyping. • Experience with system performance, throughput, latency, power, and stability testing. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.