Verification Engineer jobs in Tel Aviv-Yafo

Description For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Senior Verification Engineer to be driving into the complicated RTL design verification activity on various design aspects. Requirements Key responsibilities: • Ownership of block\cluster verification end to end from scratch. • Lead efforts of test bench architecture, Vplan definition and functional coverage. • Work closely with the design, architecture, algo teams and other stakeholders. • Support other team members and mentor less experienced engineers. Requirements • 10+ years of experience – a must • Performed at last 2 or more full block/system verification cycles. • In depth knowledge in VLSI verification flow, languages and concepts. • Experience in data path or data protocols, specifically Ethernet - preferred • Verification using one of the known methodologies (eRM, UVM, OVM). Responsibilities • Plan and perform the verification of digital design blocks according to the design specification and interacting with design engineers. • Build verification environments using SystemVerilog and UVM. • Identify and write all types of coverage measures for corner-cases. • Debug the functionality with design engineers. • Perform coverage collection and follow the metrices to close the full functionality.

Description For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Verification Team-Leader to be driving into the complicated RTL design verification activity on various design aspects. Requirements Key Responsibilities • Lead, mentor, and manage a team of verification engineers to meet project milestones and deliverables. • Define and execute verification strategies and plans for complex digital blocks and systems. • Oversee the development of robust and reusable verification environments using SystemVerilog and UVM. • Review and approve verification plans, testbenches, and coverage metrics. • Drive functional and coverage-based verification across multiple block/system verification cycles. • Collaborate with design engineers to debug and resolve functionality issues. • Ensure effective resource allocation and project planning to achieve optimal results. • Foster a culture of technical excellence, continuous learning, and innovation within the team. • Report verification progress, issues, and risks to senior management and other stakeholders. Required Qualifications • 8+ years of experience in digital design verification—a must. • 3+ years of experience managing or leading verification teams. • Proven track record of completing two or more full block/system verification cycles. • In-depth knowledge of VLSI verification flows, concepts, and methodologies. • Expertise in verification using SystemVerilog, UVM, or other industry-standard methodologies (eRM, OVM). • Experience with data protocols or data path designs (Ethernet experience preferred). • Experience with Ai, agent build, integration to flow and shorten verification cycle time. • Strong problem-solving skills and the ability to debug complex functionality issues. • Excellent leadership, communication, and organizational skills to manage and inspire a team. Preferred Qualifications • Hands-on experience with high-speed communication protocols like Ethernet, PCIe, or SerDes. • Proficiency in scripting languages (e.g., Python, Perl) for automation of verification processes. • Familiarity with formal verification techniques and tools. • Background in system-level verification or post-silicon validation. • Experience with project planning tools and methodologies for effective team management.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters. As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You won’t just execute tasks; you will define the Formal verification strategy for chips that drive the world’s largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications. Key Responsibilities • Own and develop formal verification environments from scratch through to sign-off • Apply formal verification methodologies and strategies to prove the correctness of intricate designs • Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements • Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs • Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently • Architect and develop generic, common formal functions and properties to be reused across multiple projects Basic Qualifications • Bachelor's degree in Electrical Engineering or a related technical field • 4+ years of hands-on experience in Formal Verification within semiconductor companies • Deep expertise in formal verification methodologies, tools, and flows • Strong understanding of RTL design and verification principles • Experience with industry-standard formal verification tools (Jasper, VC Formal, or similar) • Excellent communication skills, strong analytical thinking, and a proactive, "can-do" approach to problem-solving Preferred Qualifications • Track record of successfully taking complex blocks or subsystems through the entire formal verification lifecycle • Experience with SystemVerilog UVM-based design verification • Knowledge of networking standards (Ethernet, NVLink, UALink, PCIe) • Background in high-speed serial interface verification We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Job Details: Job Description: We're looking for talented, self-motivated engineers to join our Design Verification (DV) team in a junior or mid-level position. We work on some of the most technically challenging silicon in the industry, spanning digital and analog design, DSP pipelines, and firmware-hardware co-verification. What We Build Our team develops and verifies high-speed SerDes IP, the physical layer technology that moves data at speeds from 10Gbps to 100Gbps+ across PCIe, Ethernet, and other industry-standard interfaces. Getting this right matters, the world's data moves through what we build. What You'll Work On • Constrained-random and coverage-driven verification of complex high-speed SerDes mixed-signal IP, including advanced verification environment development • Validation of DSP datapaths • FW/HW joint verification • Leveraging AI-assisted tools as a core part of your daily engineering workflow What We're Looking For • Bachelor's degree in EE, CE, or CS — recent graduate with a strong academic record • Solid grasp of digital design, computer architecture, and software programming • Analytical mindset — you enjoy root-causing problems, not just finding them • Ability to thrive in a dynamic, multi-disciplinary environment • Hands-on exposure to SystemVerilog/UVM or Python — a significant advantage, but not required What We Offer • A collaborative and innovative environment where great ideas come from every level of the team • A great place to work — we take the work seriously, and each other's success personally • Exposure to the full verification lifecycle — from spec to tape-out sign-off • A team culture that embraces modern tooling, including AI-assisted engineering, as a competitive advantage • A real growth path from day one Qualifications: • Bachelor's degree in electrical engineering, Computer Engineering, or Computer Science • 0–3 years of industry or academic experience in hardware design or verificationNice to Have • Hands-on experience with SystemVerilog/UVM • Python scripting for verification automation • Familiarity with mixed-signal or analog simulation concepts • Knowledge of high-speed protocols such as PCIe or Ethernet • Prior internship or experience in RTL design or verification • Strong academic record; top graduating students are encouraged to apply Job Type: Regular Shift: Shift 1 (Israel) Primary Location: Jerusalem, Israel Additional Locations: Haifa, Israel, TLV Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Meet the Team We are a leading Design for Test (DFT) group, delivering end-to-end solutions for Cisco’s flagship products, including Cisco Silicon One. Our chips are strategically placed in critical AI infrastructure, powering next-generation network devices and supporting advanced AI workloads. We push the boundaries of technology by developing innovative DFT solutions that drive industry-leading programmability, scalability, test quality, and performance. Our team operates in a hybrid model, with three days a week in the office in Midtown Tel Aviv or Caesarea, fostering collaboration and technical excellence in a startup-like atmosphere within a stable, global corporation. Role Focus: We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the Cisco SiliconOne DFT team. This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon. Your Impact Lead and drive DFT verification activities within the Cisco SiliconOne DFT team. Develop verification plans, environments, checkers, assertions, and coverage models for DFT features. Verify DFT architecture and implementation in close collaboration with DFT, design, architecture, and verification teams. Work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features. Debug complex pre-silicon issues across RTL, verification environments, and DFT logic. Contribute to scalable methodologies, reusable verification components, and best practices for DFT DV. Help bridge between general DV methodologies and DFT-specific design and verification needs. Minimum Qualifications • B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field. • 5+ years of experience in design verification roles. • Strong experience with SystemVerilog and UVM-based verification environments. • Experience developing verification plans, coverage models, assertions, and debug flows. • Strong communication skills and ability to work closely with cross-functional teams. • Motivation to learn DFT concepts and become a key contributor in the DFT DV domain. Preferred Qualifications • Familiarity with DFT concepts such as scan insertion, memory BIST, ATPG, boundary scan, and silicon test flows. • Experience with complex SoC verification, networking silicon, or high-performance AI-driven silicon. • System-level understanding of large-scale chip architecture and integration. • Ability to build new methodologies and establish verification activity from the ground up. • High attention to detail, ownership mindset, and willingness to grow into new technical domains. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

We are now looking for a Chip Design Verification Engineer. NVIDIA is seeking a verification engineer to join the chip design methodologies team. The team is in charge of the verification methodologies, shared code, training, and embracing new technologies. One of our main goals is to make sure that the team works in an efficient manner, and provides high-quality deliveries. This position offers the opportunity to have real impact in a dynamic, technology-focused company. What you'll be doing: • Develop shared verification code and solutions to be widely used by the chip design team. • Develop groundbreaking methodologies to create a flawless experience for verification engineers to keep the focus on new problems. • Collaborate with the design automation team to provide end-to-end solutions that combine verification, simulation, and automation. • Get in touch with EDA vendors to learn about cutting-edge tools/technology and apply them into our verification process. • Understand the design, define the verification scope, develop the verification infrastructure and verify the correctness of the design. • Collaborate with designers, verification specialists to accomplish your tasks. • Develop training sessions. What we need to see: • A Bachelor's Degree in Electrical Engineering or Computer Science. • 5+ years of relevant experience • Exposure to design and verification tools. • Strong interpersonal skills and ability & desire to innovate. Ways to stand out from the crowd: • Experience in Specman / System Verilog UVM. • Understanding simulation tools. • Experience in building test benches, evaluate coverage and debug simulation failures. NVIDIA has some of the most forward-thinking and hardworking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Come join our networking verification team and help us developing great products by raising the efficiency and the quality standard in our chip design team.

We are seeking a talented and driven Senior Software Verification Engineer to join our innovative team and tackle SW verification challenges in the domains of high-speed networking, virtualization, and security. You will play a key role in validating and testing complex software products that support Ethernet and InfiniBand protocols, delivering advanced networking, storage, and security services for cloud, compute, and AI workloads. What You’ll Be Doing: • Develop and Automate Testing: Design, implement, and maintain automated test scripts and frameworks (primarily in Python) to verify the correct functionality of our software products. • End-to-End Feature Ownership: Deep dive into feature sets, taking responsibility from test planning through to final implementation and full automation. • System & Integration Validation: Validate software functionality and performance through system-level and integration testing, utilizing Linux-based environments and virtualization tools. • Test Environment Management: Set up, maintain, and optimize test environments using Linux, Docker, virtual machines, and other modern tools. • Collaboration & Communication: Work closely with software, DevOps, architecture, and product teams to define test requirements, coordinate releases, and ensure high-quality product delivery. • Continuous Improvement: Drive design verification flows, contribute to methodology improvements, and leverage planning/tracking systems to manage release progress and build release indicators. • Defect Analysis: Analyze test results, file defects, and track issues to closure, ensuring robust and scalable solutions. What We Need to See: • Bachelors/master’s degree in computer science or computer engineering, or equivalent experience • 5+ years of experience in software testing, QA automation, or software engineering. • Strong proficiency in Python and scripting for automation. • Solid experience with Linux-based environments, including system tools and command-line utilities. • Proven understanding of computer networking and modern Linux operating systems. • Familiarity with software testing, integration, and system validation practices. • Excellent problem-solving, critical thinking, and communication skills. • Ability to work independently, manage multiple tasks, and drive technical initiatives. • Great interpersonal skills, agility, and determination for success. • Fluent English; strong presentation and public speaking abilities. Ways to Stand Out from the Crowd: • Deep technical know-how and familiarity with networking protocols or low-level system tools. • Experience with Docker, KVM, or other virtualization technologies. • Knowledge of CI/CD tools (e.g., Jenkins, GitLab CI) and test reporting tools (e.g., Allure, Grafana, Kibana). • Experience with large HW+SW systems and advanced Linux OS technologies. • Proficiency with GIT, Bash, and other scripting languages. If you are creative, autonomous, and passionate about delivering world-class software solutions, we want to hear from you! Join us and work alongside some of the most forward-thinking and dedicated professionals in the industry. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

We are looking for a Formal Verification Engineer for our NVIDIA Networking team! This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking Switch and GPU technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies that are in the heart of th AI revolution. Our team delivers world class Chips solutions for HPC, AI infrastructures, data-center, network, and storage markets. We micro-architect, verify, and deliver smart and high bandwidth multi port switches. NVIDIA has the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tapeouts. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious. What you'll be doing: • In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems. • You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of NVIDIA's core technology. • You will take part in the AI revolution led by NVIDIA, working on cutting edge architecture. What we need to see: • BSc in Electrical/Computer Engineering or MSc in Mathematics • 5+ years of relevant experience in chip design field (design/verification/formal). • Excellent analytical, logical reasoning and problem-solving skills • Strong debugging and analytical skills. • Strong communication and interpersonal skills are required Ways to stand out from the crowd: • Formal verification work experience. • Knowledge of digital logic NVIDIA has some of the most forward-thinking and hardworking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Come join our team and help us build the future HPC and data centers. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer.

NVIDIA is looking for an experienced DFT Design Engineer to join the DFT design team and develop the next generation DFT technologies. As a design engineer in the DFT design team at NVIDIA, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals. What you'll be doing: • In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies. • As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production. • Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks. What we need to see: • B.Sc. in Electrical Engineering or Computer engineering or equivalent experience. • 5+ years of practical experience. • Exposure to rtl implementation and coding. • Familiarity with verification tools. • Strong debugging, problem solving and analytical skills. • Strong communication and social skills are required. • Ability to work in a geographically diverse team environment. • Self motivated, independent and target oriented. Ways to stand out from the crowd: • Prior Design or Verification experience. • Experience in developing sophisticated design blocks. • Integration of design elements to large cluster or full-chip. • Experience in working with back-end on area, power and timing closures. • Scripting ability. NVIDIA has some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of developing the next generation technologies? If so, we want to hear from you. Come, join our DFT Team for a challenging and educational environment, where every individual has a significant contribution to our products and achievements!

We are looking for a Chip Design Verification Engineer to develop the next generation of DFT technologies. As a Chip Design Verification Engineer in the DFT team at NVIDIA, you will verify the design and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and complex products. Our DFT solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals. What you'll be doing: • In this position, you will be responsible for verification of the DFT design, architecture and micro-architecture using sophisticated verification methodologies. • As a member of our DFT verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, and verify the correctness of the design. • Collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks. What we need to see: • BSc. in Electrical Engineering or Computer engineering, or equivalent experience. • 3+ years of practical verification experience. • Experience in developing verification environments and random based verification for unit level and system level using verification tools (simulation tools, Verilog, debug tools like Simvision/Debussy). • Experience with Specman is a plus. • Good understanding of RTL design (Verilog). • Strong debugging, problem solving and analytical skills. • Excellent communication and social skills. • Ability to work in a geographically diverse team environment. • Self motivated, independent and target oriented. NVIDIA has some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of developing the next generation technologies? If so, we want to hear from you. Come, join our DFT verification Team for a challenging and educational environment, where every individual has a significant contribution to our products and achievements!

Description verificationQuantum Machines is a global leader in control systems for quantum computing, a field on the verge of exponential growth. Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands. At the core of QM lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers. Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field. We are looking for a Verification Engineer who embodies ambition and positivity, who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfil the evolving needs of our expanding customer base. The Verification engineer we look for will be a highly talented and motivated person, who is a real team player and can collaborate closely with engineers from other disciplines and quantum physicists. Responsibilities: • Practicing the full range of verification aspects • Creating a verification environment from scratch (drivers, monitors, coverage...) • VIP (DDR/PCIe/AXI) integration • Defining verification sequences via a complex control-flow constraint set • System understanding of a full-stack product with strong HW-SW coupling • Reference model integration • Test plan definition • Defining verification flows and creating the proper infrastructure to support it Requirements Requirements: • At least 5 years of experience. • Ability to ramp up verification environments from scratch • Experience with UVM, System Verilog - Advantage • Knowledge of Verification IPs and protocols (PCIe, DDR, AXI) • Good understanding of HW/SW interaction- Advantage • Knowledge in C/C++/Python/System C - Advantage

Description Quantum Machines is a global leader in control systems for quantum computing, a field on the verge of exponential growth. Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands. At the core of QM lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers. Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field. We are looking for a Verification Engineer who embodies ambition and positivity, who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfil the evolving needs of our expanding customer base. The Verification engineer we look for will be a highly talented and motivated person, who is a real team player and can collaborate closely with engineers from other disciplines and quantum physicists. Responsibilities: • Practicing the full range of verification aspects • Creating a verification environment from scratch (drivers, monitors, coverage...) • VIP (DDR/PCIe/AXI) integration • Defining verification sequences via a complex control-flow constraint set • System understanding of a full-stack product with strong HW-SW coupling • Reference model integration • Test plan definition • Defining verification flows and creating the proper infrastructure to support it Requirements • 3- 5 years of experience with UVM, System Verilog. • Ability to ramp up verification environments from scratch. • Knowledge of Verification IPs and protocols (PCIe, DDR, AXI). • Good understanding of HW/SW interaction- Advantage • Knowledge in C/C++/Python/System C - Advantage