Verification Engineer jobs in Jerusalem

Job Details: Job Description: We're looking for talented, self-motivated engineers to join our Design Verification (DV) team in a junior or mid-level position. We work on some of the most technically challenging silicon in the industry, spanning digital and analog design, DSP pipelines, and firmware-hardware co-verification. What We Build Our team develops and verifies high-speed SerDes IP, the physical layer technology that moves data at speeds from 10Gbps to 100Gbps+ across PCIe, Ethernet, and other industry-standard interfaces. Getting this right matters, the world's data moves through what we build. What You'll Work On • Constrained-random and coverage-driven verification of complex high-speed SerDes mixed-signal IP, including advanced verification environment development • Validation of DSP datapaths • FW/HW joint verification • Leveraging AI-assisted tools as a core part of your daily engineering workflow What We're Looking For • Bachelor's degree in EE, CE, or CS — recent graduate with a strong academic record • Solid grasp of digital design, computer architecture, and software programming • Analytical mindset — you enjoy root-causing problems, not just finding them • Ability to thrive in a dynamic, multi-disciplinary environment • Hands-on exposure to SystemVerilog/UVM or Python — a significant advantage, but not required What We Offer • A collaborative and innovative environment where great ideas come from every level of the team • A great place to work — we take the work seriously, and each other's success personally • Exposure to the full verification lifecycle — from spec to tape-out sign-off • A team culture that embraces modern tooling, including AI-assisted engineering, as a competitive advantage • A real growth path from day one Qualifications: • Bachelor's degree in electrical engineering, Computer Engineering, or Computer Science • 0–3 years of industry or academic experience in hardware design or verificationNice to Have • Hands-on experience with SystemVerilog/UVM • Python scripting for verification automation • Familiarity with mixed-signal or analog simulation concepts • Knowledge of high-speed protocols such as PCIe or Ethernet • Prior internship or experience in RTL design or verification • Strong academic record; top graduating students are encouraged to apply Job Type: Regular Shift: Shift 1 (Israel) Primary Location: Jerusalem, Israel Additional Locations: Haifa, Israel, TLV Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Job Details: Job Description: About us: Intel Networking team delivers best in-class Ethernet products and is at the heart of Intel's transformation from a PC company to a company that powers the cloud and billions of smart, connected computing-devices. We are a team of problem solvers, experimenters, and innovators who are dedicated to designing the network technologies that currently lead and continue to transform datacenter ecosystems. As a world-class organization, we're looking for outstanding talent to accelerate our growth during an exciting time in Ethernet networking marketing technology. If you're ready to be a part of this journey, then we want to hear from you. Job Description: Verification of the microarchitecture using industry standard Formal Verification tools and technologies based on latest model checking and equivalence checking algorithms on world class design IPs. Using the hardware architecture design and RTL implementation details, define the Formal Verification scope, deploy the right strategy to prove the correctness while deploying advanced formal techniques, and create abstraction models for convergence on the design, Carve out the right boundaries for the design, create comprehensive Formal Verification test plans, track, verify, apply abstraction techniques and converge on complex designs to deliver a high quality design on schedule and articulate the ROI. analyze new methodologies, evaluates new tools and corroborate results. May work with vendors on resolving hard design and tool problems. Qualifications: Minimum Qualifications: 3+ years of experience in Formal Verification Preferred Qualifications: Experience with Jasper, SVA, Jasper Apps (connectivity, coverage) Experience with Perl/Python Experience with GHCP and AI tools Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Haifa Additional Locations: Israel, Jerusalem, Israel, Petah-Tikva Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. *