Signal & Power Integrity Engineer jobs in Israel

Job Details: Job Description: Altera, a leader in programmable solutions from cloud to edge, delivers cutting-edge FPGA, CPLD, and IP technologies. We drive innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure. Our mission is to empower engineers to design and deploy advanced systems with unmatched flexibility and performance. We are seeking a Signal and Power Engineer to join our SERDES Analog team in Haifa and support the integration of mixed-signal and high-speed SERDES IPs into full-chips silicon design, packages and PCBs. This role is ideal for early-career engineers looking to grow their hands-on design skills while working alongside experienced engineers. • SERDES IP System Simulation Support: SERDES IPs reference channel definition, creation and parameters extraction under guidance from a senior engineer • SERDES IPs Integration Support: Silicon IPs parameters review and validation with conjunction the package and PCBs design according to the interface specification • Package and PCB Design Verification: Participate in the package and PCB schematics and layouts review activities, review simulations results, and help debug and resolve failing simulations • Mixed-Signal and Channel Simulation: Learn and apply Signal and Power Integrity environments concepts, including SIPI circuits, channels and IOs simulation to support the optimisation of the package and PCB designs • Design Quality and Optimization: Support efforts to meet power, performance and signal integrity requirements, ensuring the package and PCB designs are suitable for implementation • Cross-Team Collaboration: Work with internal teams to ensure successful IPs, packages and PCBs integration and high-quality design delivery Qualifications: • B.Sc or M.Sc Electrical Engineer graduate from well recognized universities. • Strong background in electromagnetic and waves theory of physics • High motivated junior engineer with previous gathered experience from the university projects • Team players who enjoy big challenges • Ability to the study and implementation of the learned material and theory in the multidisciplinary domains: Analog and Digital Electronics, Signal and Power Integrity • Applicants must include their academic grades sheet as part of the application • Experience in ASIC package design, including optimizing pinouts, stack-ups, and high-speed routing • Knowledge of silicon floor planning, signal integrity (SI), and power integrity (PI) considerations • Hands-on experience with advanced testing and measurement equipment, including oscilloscopes and TDR/VNA analyzers • Understanding of high-speed signal design and power distribution networks (PDN) Job Type: Regular Shift: Shift 1 (Israel) Primary Location: Haifa, Israel Additional Locations: Jerusalem, Israel, TLV Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Job Details: Job Description: Job Description: Altera, a leader in programmable solutions from cloud to edge, delivers cutting-edge FPGA, CPLD, and IP technologies. We drive innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure. Our mission is to empower engineers to design and deploy advanced systems with unmatched flexibility and performance. We are seeking a Student/Junior Signal and Power Engineer to join our SERDES Analog team in Haifa and support the integration of mixed-signal and high-speed SERDES IPs into full-chips silicon design, packages and PCBs. This role is ideal for early-career engineers looking to grow their hands-on design skills while working alongside experienced engineers. Responsibilities • SERDES IP System Simulation Support: SERDES IPs reference channel definition, creation and parameters extraction under guidance from a senior engineer • SERDES IPs Integration Support: Silicon IPs parameters review and validation with conjunction the package and PCBs design according to the interface specification • Package and PCB Design Verification: Participate in the package and PCB schematics and layouts review activities, review simulations results, and help debug and resolve failing simulations • Mixed-Signal and Channel Simulation: Learn and apply Signal and Power Integrity environments concepts, including SIPI circuits, channels and IOs simulation to support the optimisation of the package and PCB designs • Design Quality and Optimization: Support efforts to meet power, performance and signal integrity requirements, ensuring the package and PCB designs are suitable for implementation • Cross-Team Collaboration: Work with internal teams to ensure successful IPs, packages and PCBs integration and high-quality design delivery Qualifications: Minimum Qualifications • B.Sc or M.Sc Electrical Engineer at well recognised universities with average grades above 85with one years till graduation • Strong background in electromagnetic and waves theory of physics • High motivated junior engineer with previous gathered experience from the university projects • Team players who enjoy big challenges • Ability to the study and implementation of the learned material and theory in the multidisciplinary domains: Analog and Digital Electronics, Signal and Power Integrity • Applicants must include their academic grades sheet as part of the application Preferred Qualifications for the Student • Basic or deep knowledge in Keysight ADS and HSPICE simulation setup creation and running • Basic or deep hands-on experience in the Ansys HFSS, Cadence Clarity or similar Electromagnetic Simulation tools – setups creation and parameters definition, simulation running • Basic or deep knowledge of the PCIe and IEEE Ethernet specification ---This is a student position which is relevant for Israel Only--- Job Type: Student / Intern (Fixed Term) Shift: Shift 1 (Israel) Primary Location: Haifa, Israel Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position  We are looking for a Senior Signal Integrity (SI) and Power Integrity (PI) Engineer to own end-to-end electrical link performance across our high-speed interconnects - from architecture and pre-silicon modeling through silicon bring-up, validation, and high-volume manufacturing (HVM). This is a hands-on technical role for someone who has taken multiple products from concept to production and knows what breaks (and why) once real volume hits the line. Responsibilities  • Own signal integrity and power integrity analysis for end-to-end high-speed links, including package, connector, PCB, and cable interconnects • Drive SI/PI closure for high-speed SerDes interfaces (112G/224G-class), PCIe (Gen5/Gen6+), and parallel/single-ended interfaces such as DDR/LPDDR memory and chip-to-chip links • Perform pre-silicon channel modeling, budgeting, and margin analysis using COM (Channel Operating Margin), IBIS-AMI, and statistical eye methodologies • Build and correlate 3D/2.5D EM models (HFSS, PowerSI) against lab measurement (VNA, TDR, BERT, scope) to validate channel and package performance • Perform system-level power delivery network (PDN) analysis, decoupling strategy, and power/SI co-design across chip, package, and board • Use ADS and MATLAB for circuit-level simulation, link budget analysis, and custom post-processing/automation of simulation and lab data • Support silicon bring-up, debug, and characterization in the lab; root-cause SI/PI-related failures and drive corrective actions • Partner with ASIC, package, PCB layout, and mechanical teams to define design rules, stackups, routing guidelines, and connector/material selection • Lead products through DVT/PVT and into high-volume manufacturing, including establishing test limits, correlating ATE/system-level test data to simulation, and resolving field/yield issues tied to SI/PI margin • Contribute to internal methodology, tooling, and design guideline development. Requirements • 10+ years of hands-on SI/PI engineering experience in the semiconductor, systems, or networking hardware industry • Demonstrated experience across the full product lifecycle — architecture through production and sustained high-volume manufacturing — not just simulation-only roles • Deep working knowledge of high-speed SerDes signaling, including 224G (or comparable leading-edge) electrical interfaces, and PCIe link architecture • Solid experience with parallel/source-synchronous interfaces such as DDR/memory buses and chip-to-chip interconnects • Proficiency with COM-based analysis and IBIS-AMI modeling for channel compliance and margin assessment • Strong command of industry-standard tools: Ansys HFSS, Ansys PowerSI (or equivalent 2.5D/3D field solvers), Keysight ADS, and MATLAB • Hands-on proficiency with SI/PI lab testing and validation equipment, including Vector Network Analyzers (VNA) for S-parameter extraction, TDR/TDT for impedance and discontinuity characterization, and oscilloscopes for eye diagram, jitter, and signal quality measurement • Familiarity with power integrity fundamentals — PDN impedance analysis, decap strategy, DC/AC drop, and chip-package-board co-design • Experience working with cross-functional teams (ASIC design, package engineering, PCB layout, test/ATE, manufacturing) to drive designs to closure • Excellent written and verbal communication skills; able to clearly present technical risk and trade-offs to both engineering and program stakeholders Preferred Qualifications  • Experience with additional high-speed standards (CXL, Ethernet SerDes) • Scripting/automation experience (Python) for simulation flow automation or data analysis • Experience with connector, cable, or optical module electrical characterization • Familiarity with signal/power co-simulation and chip-package-system (CPS) modeling flows • Exposure to compliance testing and industry standards bodies (PCI-SIG, OIF-CEI, JEDEC) We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!

We are looking for Senior Signal & Power Integrity Engineer. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence! We work closely with NVIDIA sites in USA and China and have access to extensive knowledge, technologies and tools. Taking the products from concepting, through design, implementation, verification and release to customers. If you thrive working with highly skilled people that enjoy reaching challenging goals then NVIDIA might be the perfect workplace for you. This is a dynamic team working with state of the art, unique technology. If you are someone that loves a challenge, come join this diverse team and help move the needle ! What you'll be doing: • Design low-speed I/O channels such as clock circuits, DDR/memories and other sensitive signals. • Design layout guidelines for our packages and PCBs (for switches, adapters and electro-optical modules). • Design package/board/system SI/PI design activities, including PCB stack-up/material selection, design guide implementation, layout review and post-layout analysis. • Work closely with Architecture, ASIC, Mixed Signal, Package, and PCB design teams to design and ensure system SI/PI performance meets expectation. • Simulate passive and active elements in 3D and 2D simulation tools. • Measure systems in the lab using Network Analyzer, TDR and scope. • Work in an intense environment and control multi-discipline expertise What we need to see: • B.Sc. in Electrical Engineering (or equivalent experience) • 5+ years of experience • Expert with low-speed I/O simulations and design concepts including clock circuits, DDR/memories , transmitter & receiver design and equalization schemes. • Expert level proficiency with time domain analysis and tools. • Excellent understanding in electromagnetic waves including transmission line theory and via properties. • High level proficiency with electromagnetic tools (such as Ansys EM, CST, etc.) • Experience in Lab measurements including VNA & TDR. • Ability to work in an intense environment and control multi-discipline expertise. Ways to stand out from the crowd: • M.Sc./Ph.D. in Electrical Engineering. • Expert with time domain co-simulation of I/O circuits and PDN models. • Familiar with NRZ/PAM-4 signaling schemes. • Experience with MATLAB, Python, and C. With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our exclusive engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence! We are looking for a Senior Signal & Power Integrity Engineer. We work closely with NVIDIA sites in USA and China and have access to extensive knowledge, technologies and tools. Yet we are responsible for our own product line of PHY IC’s . Taking the products from concepting, through design, implementation, verification and release to customers. If you thrive working with highly skilled people that enjoy reaching challenging goals then NVIDIA in might be the perfect workplace for you. This is a dynamic team working with state of the art, unique technology. If you are someone that loves a challenge, come join this diverse team and help move the needle ! What you'll be doing: • Design high frequencies channels up to 400Gb/s per lane for PCBs, packages, connectors and cables. • Design layout guidelines for our systems. • Simulate passive and active elements in 3D and 2D simulation tools • Measure systems in the lab using Network Analyzer, TDR and scope • Master InfiniBand, Ethernet and PCI-Ex Layer 1 specifications and implementation methods • Work in an intense environment and control multi-discipline expertise What we need to see: • B.Sc. in Electrical Engineering (or equivalent experience) • 5+ years of experience • Familiar with electromagnetics, specifically electromagnetic waves including transmission line theory and via properties. • Expert level proficiency with EM tools (such as Ansys EM, CST, etc.). • Familiarity with high-speed I/O design concepts including clock generation, transmitter & receiver design, and equalization schemes. • Experience in Lab measurements including VNA & TDR experience, interface timing budgets, and system modeling. • Master InfiniBand, Ethernet, and PCI-Ex Layer 1 specifications and implementation methods. • Ability to work in an intense environment and control multi-discipline expertise. Ways to stand out from the crowd: • M.Sc./Ph.D. in Electrical Engineering and PDN analyses including model generation and time domain simulation. • Familiar with NRZ/PAM-4 signaling schemes. • Analyses involving co-simulation of circuits and PDN models. • Experience with MATLAB, Python, and C. • Exposure to TSV (Through-Silicon-Via) modeling and analysis. With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our exclusive engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.