Power Integrity Engineer jobs in Ra'anana

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position  We are seeking a highly skilled Senior Power Engineer to take a leadership role in defining the board-level and rack-level power delivery architecture for our next-generation, multi-kilowatt AI server platforms. This critical position owns the end-to-end design of high-current power delivery paths to advanced SoCs, encompassing the definition of voltage conversion and regulator strategy, comprehensive Power Delivery Network design including efficient decoupling schemes, and driving critical design tradeoffs to maximize efficiency, optimize thermal performance, and ensure overall system performance, all while considering compatibility with OCP/Open Rack power distribution standards. You will work cross-functionally with silicon, mechanical, thermal, and systems engineers to deliver robust, efficient, and scalable power delivery for these complex platforms. Responsibilities  • Architect and design board-level, server-level, and rack-level power delivery systems for high-power subsystems. • Define PDN topology, including VRMs, POLs, vertical and lateral power routing, and high-current interfaces. • Perform component selection (VRMs, FETs, inductors, bulk caps, MLCCs, connectors, busbars) and create derating, margin, and reliability guidelines. • Lead decoupling capacitor strategy across package and PCB layers to meet target impedance and transient response goals. • Drive power integrity analysis (AC/DC, Z-target, transient, EMI/EMC) and validate designs through modeling, simulation, and lab measurement. • Collaborate with mechanical and thermal teams to ensure high-current routing, cooling requirements, and system constraints are aligned. • Partner with silicon and package engineering to co-design vertical PDN paths, including socket interfaces, pin/bump maps, and transient load profiles. Review and advise silicon design to improve power integrity. • Develop test plans for PDN validation, transient load tests, impedance measurement, and system bring-up. • Provide expertise during failure analysis, root-cause investigations, and corrective actions for system power issues. Requirements • BS/MS in Electrical Engineering or related field. • 10+ years of experience in high-power delivery design. • Demonstrated experience designing high-current, low-voltage power delivery for SoCs. • Deep expertise in power integrity, PDN modeling, VRM design, target impedance definition, and transient response optimization. • Proficiency with SPICE, PDN simulation tools (Keysight, Cadence Sigrity/Clarity, Ansys SIwave), and measurement equipment (VNAs, oscilloscopes, electronic loads). • Solid understanding of package-to-PCB PDN interactions. • Strong communication and cross-functional collaboration skills. Preferred Qualifications  • Familiarity with EMI/EMC mitigation in high-current environments. • Experience in server-class PCB design, including stackup planning, high-current routing, and decoupling strategies • Background in thermal-mechanical co-design for high-power modules. • Knowledge of rack-level power architectures, ORv3/OCP standards, power shelves, and busbar system We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!

Description Senior Power Integrity Engineer #LI-Hybrid About DriveNets DriveNets is a leader in high-scale networking software for AI infrastructure and service providers. The company pioneered a disaggregated networking architecture that transforms the economics of large-scale networks while maximizing performance, utilization, and operational efficiency. DriveNets-powered networks are deployed by global leaders, including AT&T and Comcast, supporting more than 30% of total U.S. internet traffic. DriveNets AI Fabric delivers full-stack networking for AI infrastructures, providing the highest-performance, Ethernet-based alternative to InfiniBand. The solution is deployed by hyperscalers, NeoClouds, and enterprises worldwide. With over $1B raised, DriveNets continues to push the boundaries of modern networking infrastructure. The Role DriveNets is seeking a highly motivated Power Integrity Engineer to join our Hardware Engineering team. In this role, you will be responsible for defining, analyzing, simulating, and validating power delivery networks (PDNs) for next-generation networking platforms supporting high-performance ASICs, advanced SerDes interfaces, optical modules, and AI-scale networking systems. You will work closely with hardware architects, PCB designers, ASIC teams, signal integrity engineers, mechanical engineers, and manufacturing partners to ensure robust power delivery, optimal system performance, and successful product deployment. Responsibilities • Lead Power Integrity (PI) activities throughout the hardware development lifecycle, from architecture through production. • Define and optimize board-level and package-level Power Delivery Networks (PDNs) for high-current networking ASICs and supporting devices. • Perform pre-layout and post-layout PI simulations using industry-standard tools. • Establish target impedance requirements and validate compliance across all power rails. • Analyze DC voltage drop, AC impedance, transient response, and power distribution performance. • Collaborate with PCB layout engineers to optimize stackups, plane structures, decoupling strategies, and power routing. • Work closely with Signal Integrity engineers to ensure SI/PI co-optimization of high-speed interfaces. • Develop power integrity design guidelines and best practices for next-generation networking products. • Support schematic reviews, layout reviews, and design sign-off activities. • Perform laboratory measurements and correlation using oscilloscopes, VNAs, power analyzers, current probes, and related equipment. • Investigate and resolve PI-related issues during board bring-up, validation, and production. • Collaborate with ASIC, FPGA, memory, optics, and power component vendors to optimize overall system performance. • Drive continuous improvement of PI methodologies, simulation flows, and validation processes. Why Join DriveNets • Work on industry-leading networking systems deployed by top-tier service providers and cloud operators. • Influence next-generation networking hardware architecture. • Collaborate with world-class hardware, ASIC, and software engineers. • Be part of a fast-growing company transforming the networking industry Requirements • B.Sc. or M.Sc. in Electrical Engineering. • 5+ years of experience in Power Integrity, Hardware Design, or related disciplines. • Strong understanding of power delivery networks, decoupling methodologies, and target impedance concepts. • Hands-on experience with PI simulation tools such as: • Cadence Sigrity PowerSI / OptimizePI • Ansys SIwave • Ansys HFSS • PowerDC or equivalent • Experience designing high-layer-count PCBs for networking, telecom, server, or data-center products. • Knowledge of high-speed digital systems and interaction between Signal Integrity and Power Integrity. • Experience with multi-phase voltage regulators, power sequencing, and power management architectures. • Strong understanding of PCB materials, stackups, and manufacturing constraints. • Experience performing lab validation and correlation measurements. • Excellent problem-solving, communication, and teamwork skills. Preferred Qualifications • Experience with high-performance networking ASICs and switch silicon. • Familiarity with 112G/224G/448G PAM4 SerDes technologies. • Experience with Ethernet systems ranging from 400G to 1.6T and above. • Understanding of package-level PI and advanced packaging technologies. • Familiarity with optical networking platforms and co-packaged optics. • Experience with thermal and mechanical effects on PDN performance. • Knowledge of EMI/EMC considerations in high-density networking systems. • Experience working with ODMs, CMs, and global manufacturing partners. Success Metrics • Achieve PI sign-off requirements for all networking platforms. • Minimize power-related issues during bring-up and production. • Improve first-pass hardware success rate. • Enable reliable operation of next-generation high-bandwidth networking systems. • Establish scalable PI methodologies for future DriveNets hardware platforms. More About DriveNets Based in Israel with locations in Romania, US, India and Japan as well as extended teams, DriveNets operations cover more than twelve countries. With recognition by industry analysts and through partnerships with market leaders such as AMD, Broadcom, Dell and others, DriveNets is pushing market momentum, delivering the scale and efficiency that modern AI workloads demand. Visit our website: https://drivenets.com/company/