Power Engineer jobs in Yokneam

Our team in Yokneam, Israel is looking for a Senior Power Integrity Engineer to join the Hardware Board Design team and lead PI development of next-generation Network Adapters for high-speed communication products. NVIDIA’s Networking division delivers end-to-end InfiniBand and Ethernet connectivity for servers and storage, including adapter cards, switches, cables and software that power data centers, cloud, big data, Web 2.0 and high-performance computing workloads. What you'll be doing: • Lead PI definition and implementation for board-level designs, from concept and architecture through validation, qualification and release to production. • Define the power core architecture and requirements and serve as the technical lead for all power-related performance and debug activities • Work closely with power supply vendors to align solutions with NVIDIA product needs, and build and optimize configuration files for programmable regulators. • Own power delivery network (PDN) design for complex network adapter boards, including rail partitioning, decoupling strategy, VR selection and dynamic load support. • Perform system-level power integrity simulations (frequency and time domain) and co-simulation of circuits and PDN models to predict noise. • Create and maintain board PI design guidelines: stackup, materials, breakout, routing, decoupling and placement rules for layout teams and external partners. • Use advanced 2D/3D EM tools to model and optimize vias, planes, connectors, sockets and other interconnect elements for power integrity. • Perform lab characterization and correlation using VNA, TDR and high‑bandwidth oscilloscopes; refine models and design rules based on measurement data. What we need to see: • B.Sc. in Electrical Engineering (or equivalent experience). • 5+ years of industry experience in signal and/or power integrity for high-speed board or system designs. • Strong understanding of electromagnetics, transmission line theory, PDN behavior and their application. • Expert-level proficiency with EM and PI tools (for example, Ansys HFSS/Q3D/SIwave, CST, or equivalent) and SPICE-based time-domain simulations. • Proven experience in PDN analysis, including model generation, impedance targets, resonance mitigation and time-domain noise simulations. • Hands-on lab experience with VNA, TDR and oscilloscopes for PI/SI validation, de-embedding and model correlation. • Ability to work independently in an intense, multi-disciplinary environment with strong ownership and excellent interpersonal skills. Ways to stand out from the crowd: • Deep experience designing PDNs for complex multilayer boards with high-current, low-voltage rails supporting advanced networking or compute ASICs. • Demonstrated background in PI co-simulation flows, PSIJ analysis and end-to-end system modeling (die–package–board). • Experience with scripting and data analysis using MATLAB, Python or C for simulation automation and large-signal data processing. • Exposure to advanced packaging and interconnect technologies (for example, TSV, high-speed connectors, advanced laminates). • Practical knowledge of PCB fabrication, product qualification flows and lab debug of complex high-speed boards. NVIDIA is widely considered to be one of the technology world’s most desirable employers, with some of the most talented and forward-thinking individuals working together on groundbreaking products and services. We are committed to fostering a diverse and inclusive work environment and are proud to be an equal opportunity employer that does not discriminate on any legally protected basis. If you are a creative and autonomous engineer with a real passion for power and signal integrity in cutting-edge networking systems, we want to hear from you.

We are now looking for a Power Optimization and Analysis Engineer! NVIDIA prides ourselves on having energy-efficient products. We believe that continuing to maintain our products' energy-efficiency compared to competition is key to our continued success. As part of the u/arch team in the Switch group, you will be responsible for analyzing full chip and unit-level power data and driving the FE/BE ASIC teams to improve their units’ power efficiency; you will be responsible for researching, developing, and deploying methodologies to help NVIDIA's products become more energy efficient. Key responsibilities include developing techniques to model, analyze, and reduce power consumption of NVIDIA Switches product line. As a member of Switch u/arch Team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement power analysis and reduction techniques for NVIDIA's next generation switches. Your contributions will help us gain early insight into energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements. What You'll Be Doing: • Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency. • Develop and share best practices for performing pre-silicon power analysis. • Perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny. • Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes. • Select and run a wide variety of workloads for power analysis. • Prototype new architectural features in Verilog and power analysis. What We Need To See: • BSC or MS in Computer Engineering or Electrical Engineering • 5+ years of experience in chip design • Good and interpersonal skills; much collaboration with design teams is expected. • Familiarity with Verilog and ASIC design or verification. • Desire to bring data-driven decision-making and analytics to improve our products. • Strong coding/automation skills, preferably in Python, Perl, and C++. Ways to Stand Out From the Crowd: • Experience with Power Artist, PTPX (Prime Power RTL, RTL Architect). • Strong understanding of concepts of energy consumption, estimation, data movement and low power design.