Physical Design Engineer jobs in Israel

Description For an exciting well-funded start-up, we are looking for a Backend Team member. You will work on complex design, high frequency and low-power budget. Work on ramp-up full RTL2GDSII flow for leading technology and work with external vendors. Requirements Key responsibilities: • RTL-to-GDSII Ownership: execute the complete backend implementation flow (Logic Synthesis, P&R, Tape-Out, IR-drop, etc.), ensuring timely, first-pass silicon success. · Constraints & Timing Closure: Work with design and DFT engineers to write timing and physical constraints, and sign-off on the design using comprehensive Static Timing Analysis (STA), timing eco implementation. · Advanced Physical Implementation: Drive complex physical design tasks including Floorplanning, Power/Ground (PG) Mesh implementation, and handling advanced clocking (CTS/Clock-Mesh) and Hierarchical Design flows. · Low Power Expertise: Define, implement, and verify advanced low power design techniques to meet aggressive power consumption targets. · Design for Manufacturability: Implement and verify Design-for-Test (DFT) strategies and close physical verification challenges, specifically focusing on IR-Drop analysis. · IP Integration & Automation: Execute complex IP integration, incorporating blocks generated by memory compilers and other automated tools. • Collaboration: work closely with design team to understand the data path and correctly implement the floorplan, provide feedback on RTL changes required, Implement logical eco post RTL freeze with design team. • CAD: Improve existing implementation flows to achieve better QOR, write scripts for supporting the P&R flows. Minimum Qualifications • Experience of 5+ years in backend design • Strong expertise of full RTL2GDSII including: • Logic synthesis & equivalence checking • Constraints definition and writing • Complicated IP integration • Memory compilers and other automated block generators • DFT • Floorplanning, PG Mesh • P&R • Low power design including definition, implementation and verification • Timing STA • IR-Drop • BS/MS in EE/CE from lead universities Preferred Qualifications • Team player • Highly motivated • Learning abilities • Good communication • Work with external vendors • Experience in Synopsys/Cadence tools is an advantage • Low power techniques • Clock-mesh/ multi source cts • Hierarchical design flow • Experience in tape-out procedures • RTL code reading A very interesting job and good conditions are guaranteed to the candidates

Description For an exciting well-funded start-up, we are looking for a Backend Team member. You will work on complex design, high frequency and low-power budget. Work on ramp-up full RTL2GDSII flow for leading technology and work with external vendors. Requirements Key responsibilities: • RTL-to-GDSII Ownership: execute the complete backend implementation flow (Logic Synthesis, P&R, Tape-Out, IR-drop, etc.), ensuring timely, first-pass silicon success. · Constraints & Timing Closure: Work with design and DFT engineers to write timing and physical constraints, and sign-off on the design using comprehensive Static Timing Analysis (STA), timing eco implementation. · Advanced Physical Implementation: Drive complex physical design tasks including Floorplanning, Power/Ground (PG) Mesh implementation, and handling advanced clocking (CTS/Clock-Mesh) and Hierarchical Design flows. · Low Power Expertise: Define, implement, and verify advanced low power design techniques to meet aggressive power consumption targets. · Design for Manufacturability: Implement and verify Design-for-Test (DFT) strategies and close physical verification challenges, specifically focusing on IR-Drop analysis. · IP Integration & Automation: Execute complex IP integration, incorporating blocks generated by memory compilers and other automated tools. • Collaboration: work closely with design team to understand the data path and correctly implement the floorplan, provide feedback on RTL changes required, Implement logical eco post RTL freeze with design team. • CAD: Improve existing implementation flows to achieve better QOR, write scripts for supporting the P&R flows. Minimum Qualifications • Experience of 10+ years in backend design • Strong expertise of full RTL2GDSII including: • Logic synthesis & equivalence checking • Constraints definition and writing • Complicated IP integration • Memory compilers and other automated block generators • DFT • Floorplanning, PG Mesh • P&R • Low power design including definition, implementation and verification • Timing STA • IR-Drop • BS/MS in EE/CE from lead universities Preferred Qualifications • Team player • Highly motivated • Learning abilities • Good communication • Work with external vendors • Experience in Synopsys/Cadence tools is an advantage • Low power techniques • Clock-mesh/ multi source cts • Hierarchical design flow • Experience in tape-out procedures • RTL code reading A very interesting job and good conditions are guaranteed to the candidates

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Location: Tel-Aviv or Caesarea, Israel, Hybrid Start date: As soon as possible Applications accepted until further notice Who We Are The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. What You'll Do You'll be joining our Physical Design team at Cisco Silicon One, which is at the center of the silicon development at Cisco. Our engineers deal with all chip design aspects: definition, architecture, micro-architecture, design, verification, signoff and validation. We use the latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility. Minimum Qualifications • B.Sc or M.Sc Electrical Engineering or Computer Engineering graduate from leading Israeli Universities. • GPA above 87 (Please attach your grade sheet when applying to expedite the recruitment process). • You are an ambitious and motivated individual, who enjoys big challenges and can quickly ramp on multiple domains. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

NVIDIA is looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • You will be developing physical design, STA, Logic eq, Power Integrity flows and methodologies for implementation of networking chips and SOCs. • Work closely with block owners, full Chip STA engineers to assure high quality and timely convergence. • Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips. • Additional responsibilities include participating and developing flow and tool methodologies for timing analysis and closure, power and noise analysis, IR-drop, EM and back-end verification across multiple projects. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience). • 2+ years of fulltime relevant experience in the areas listed below. • Proven experience and strong knowledge in key technical domains, including: Physical Design, STA (Static Timing Analysis) and Timing closure methodologies. • Familiarity with industry-standard tools like PrimeTime (STA) and PrimePower (Power Estimation). • Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role. • Strong sense of ownership, self-learning skills, and ability to work both independently and collaboratively with internal and global teams Ways to stand out from the crowd: • Experience in Signoff domains: STA (PrimeTime), Power Estimation (PrimePower), Power Integrity (RedHawk), Formal eq. (Formality), Backend CAD (Computer-Aided Design), • Knowledge in Tcl/Perl/Python • Versatile • Great teammate NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry! #LI-Hybrid

NVIDIA is looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • You will be developing physical design, STA, Logic eq, Power Integrity flows and methodologies for implementation of networking chips and SOCs. • Work closely with block owners, full Chip STA engineers to assure high quality and timely convergence. • Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips. • Additional responsibilities include participating and developing flow and tool methodologies for timing analysis and closure, power and noise analysis, IR-drop, EM and back-end verification across multiple projects. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience). • 2+ years of fulltime relevant experience in the areas listed below. • Proven experience and strong knowledge in key technical domains, including: Physical Design, Backend CAD (Computer-Aided Design), STA (Static Timing Analysis) and Timing closure methodologies. • Familiarity with industry-standard tools like PrimeTime (STA) and PrimePower (Power Estimation). • Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role. • Strong sense of ownership, self-learning skills, and ability to work both independently and collaboratively with internal and global teams Ways to stand out from the crowd: • Experience in Signoff domains: STA (PrimeTime), Power Estimation (PrimePower), Power Integrity (RedHawk), Formal eq. (Formality) • Knowledge in Tcl/Perl/Python • Versatile • Great teammate NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry! #LI-Hybrid

NVIDIA is looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: • You will be in charge of developing physical design, synthesis, STA and Logic eq methodologies for implementation of networking chips and SOCs. • Work closely with block owners. full Chip STA engineers and project managers to assure high quality and timely convergence. • Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips. • Additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects. What we need to see: • B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience). • At least 2 years of relevant experience • Proficiency using Python, Perl, Tcl, Make scripting. • Expertise in analysing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes. • Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power required and implementing them through ECOs is required. • Knowledge in process variation effect modelling and experience in design convergence taking into account variations. • Successful track record of delivering designs to production is necessary. • Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role. Ways to stand out from the crowd: • Familiarity with synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Innovus/Tempus) • Experience in methodology definition / flow owner of synthesis / Place and Route/ STA steps is an advantage. • Great teammate. • Ownership, self-learning skills, and ability to work autonomously. NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry! #LI-Hybrid

Job Details: Job Description: Our team is dedicated to optimizing Intel’s cutting-edge process technology to meet the rapidly evolving needs of next-generation silicon designs. Operating at the intersection of process and design development, we drive continuous innovation in both physical design and methodology. We partner closely with Core and SoC design teams worldwide to drive both process and product-level optimization - directly enabling Intel to deliver highly competitive, high-performance and low-power products. Role Overview As a Physical Design & PPA Optimization Engineer, you will play a key role in achieving best-in-class Power, Performance, and Area (PPA) for Intel IPs. You will be responsible for identifying optimization opportunities, developing physical design optimization methodologies, executing the full physical design flow to evaluate PPA landing zones on new Intel process technologies, and translating findings into actionable recommendations that influence strategic decision-making and product direction. Key Responsibilities • Define and implement DTCO experiments to evaluate the interaction between process technology and physical design implementation. • Define and develop design optimization methodologies across all physical design flow domains, such as placement, CTS, routing, and timing closure • Run the full PnR flow to evaluate new technology impacts on PPA metrics. • Identify trade-offs and optimization opportunities at the device, cell, and block Qualifications: Minimum Qualifications • BSc or MSc in Electrical Engineering, Computer Engineering, or a related field • Hands-on experience in physical or circuit design • Basic scripting experience using Python, Tcl, or a similar language • Strong analytical and problem-solving skills • Ability to analyze implementation results and communicate conclusions clearly Preferred Qualifications • 2+ years of experience in physical design or circuit design • Familiarity with physical design implementation flows and methodologies • Solid understanding of transistor, cell, and block-level PPA trade-offs • Experience developing physical design methodologies and analysis tools #LI-DL1 Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Haifa Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *