Mixed Signal Verification Engineer jobs in Ramat Gan

Description For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Mixed signal verification engineer. Requirements Key Responsibilities: • Develop verification strategies for digital and analog (mixed-signal) designs, utilizing UVM methodologies based on specifications. • Create behavioural models for analog blocks in accordance with guidelines provided by analog designers. • Write, execute, and debug testbenches using UVM methodology and SystemVerilog code for mixed-signal blocks. • Run and debug behavioural model (BM) validation using AMS tools to ensure the correctness of the behavioural models. • Perform and troubleshoot unit-level, cluster-level and top-level simulations of mixed-signal designs. Minimum Qualifications • 5+ years of experience • Experience in Behavioural Modelling (BM) of Analog design for digital verification • Knowledge in Mixed Signals dynamic Verification using chip digital design tools [no AMS] • Experience in Verilog/SystemVerilog coding • Experience in Virtuoso Schematics tools • Basic knowledge in Analog design Preferred Qualifications • Experience in UVM • Experience in both Synopsys and Cadence tools is an advantage Additional Skills • Verification Methodologies and Tools: Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases. • Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative team environment. • Communication: Strong communication skills, including the ability to write test plans, present results, and communicate clearly with multi-functional teams.

Description For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Mixed signal verification engineer. Requirements Key Responsibilities: • Develop verification strategies for digital and analog (mixed-signal) designs, utilizing UVM methodologies based on specifications. • Create behavioural models for analog blocks in accordance with guidelines provided by analog designers. • Write, execute, and debug testbenches using UVM methodology and SystemVerilog code for mixed-signal blocks. • Run and debug behavioural model (BM) validation using AMS tools to ensure the correctness of the behavioural models. • Perform and troubleshoot unit-level, cluster-level and top-level simulations of mixed-signal designs. Minimum Qualifications • 10+ years of experience • Experience in Behavioural Modelling (BM) of Analog design for digital verification • Knowledge in Mixed Signals dynamic Verification using chip digital design tools [no AMS] • Experience in Verilog/SystemVerilog coding • Experience in Virtuoso Schematics tools • Basic knowledge in Analog design Preferred Qualifications • Experience in UVM • Experience in both Synopsys and Cadence tools is an advantage Additional Skills • Verification Methodologies and Tools: Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases. • Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative team environment. • Communication: Strong communication skills, including the ability to write test plans, present results, and communicate clearly with multi-functional teams.

Description For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Mixed signal verification Tean-Lead. Requirements • Lead and manage a distributed team of mixed-signal verification engineers across different time zones, ensuring smooth communication and collaboration. • Collaborate with analog and digital design teams to establish specifications, verification plans, and key milestones. • Define and oversee the development of behavioral models (BM) of analog designs, integrating them into digital verification flows. • Drive the execution of mixed-signal dynamic verification using industry-standard digital verification tools (excluding AMS). • Debug and resolve complex issues in mixed-signal designs, ensuring functionality and specification compliance. • Plan and implement scalable and reusable verification environments using Verilog/SystemVerilog. • Provide mentorship and technical guidance to team members, supporting their professional growth. • Manage project timelines, resource allocation, and reporting to ensure successful delivery of verification goals. Minimum Qualifications • 8+ years of experience in mixed-signal and/or digital mixed signal verification. • 3+ years of experience managing or leading verification teams. • Proven experience in Behavioral Modeling (BM) of analog designs for digital verification. • Expertise in mixed-signal dynamic verification using digital verification tools (excluding AMS). • Knowledge Verilog/SystemVerilog for building and debugging testbenches. • Experience with Virtuoso for analog schematic understanding and review. • Solid understanding of analog design fundamentals and concepts. Preferred Qualifications • Hands-on experience with UVM methodology. • Proficiency in both Synopsys or Cadence verification tools. Additional Skills • Verification Methodologies and Tools: Proven ability to develop scalable, portable test cases and utilize verification tools effectively, including simulators, waveform viewers, and coverage collection. • Collaborative Environment: Experience verifying analog/mixed-signal designs in a cross-functional, team-oriented setting. • Communication: Exceptional skills in writing test plans, presenting results, and communicating effectively with multi-disciplinary teams and stakeholders.