Logic Design Engineer jobs in Israel

Description NextSilicon is reimagining high-performance computing (HPC & AI). Our accelerated compute solutions leverage intelligent adaptive algorithms to vastly accelerate supercomputers, driving them forward into a new generation. We have developed a novel software-defined hardware architecture that is achieving significant advancements in both the HPC and AI domains. NextSilicon is looking for a talented and experienced engineer to participate in designing the next era of computer architecture. In this position you will take part in designing the critical parts of NextSilicon’s future chips. You will transform architectural requirements to micro-architectural specs, implement key blocks in RTL, and participate in post-silicon activities. At NextSilicon, everything we do is guided by three core values: • Professionalism: We strive for exceptional results through professionalism and unwavering dedication to quality and performance. • Unity: Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard. • Impact: We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide. Requirements • B.Sc. in Electrical Engineering or Computer Science • 5+ years of digital design experience with complex blocks • Ability to transform requirements into specification documents • Proven record in complex design • Experience in front-end tools and analysis: CDC, LINT, power, simulation • Team player, versatile and results-oriented • Experience in Floating-Point Unit is an advantage Responsibilities • Define and drive the design of advanced blocks from micro-architecture phase to netlist • Support timing and constraints definitions work closely with the BE team on timing and physical implementation efforts • Leading processes relating to power optimization • Technology expert, building a knowledge base for the group • Work with various teams to drive execution (SW, Architecture, verification, BE, etc) • Devise execution indicators and monitor and report execution progress to enable prioritization and clear decision making

Description NextSilicon is reimagining high-performance computing (HPC & AI). Our accelerated compute solutions leverage intelligent adaptive algorithms to vastly accelerate supercomputers, driving them forward into a new generation. We have developed a novel software-defined hardware architecture that is achieving significant advancements in both the HPC and AI domains. At NextSilicon, everything we do is guided by three core values: • Professionalism: We strive for exceptional results through professionalism and unwavering dedication to quality and performance. • Unity: Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard. • Impact: We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide. • NextSilicon is looking for a talented and experienced Logic Design Group Lead to drive and help our group to get to the next era of computer architecture. In this position, you will lead the architecture of NextSilicon’s future chips, driving system-level understanding and the overall architectural flow. You will manage managers and technical leads while remaining highly hands-on, taking an active role in architectural decisions and technical execution across the system. Requirements • B.Sc. in Electrical Engineering or Computer Science • 8+ years of digital design experience with complex blocks • 5+ years as a design team leader • Ability to transform requirements into specification documents • Proven record in high-speed and low-power design • Experience in front-end tools and analysis: CDC, LINT, power, simulation • Experience in network design or compute is an advantage Responsibilities • Be accountable for your group's milestones & timelines • Leading your Group Architecture and developing their abilities • Technology expert, building a knowledge base for the group • Work with various teams to drive execution (SW, Architecture, verification, BE, etc) • Devise execution indicators, monitor and report execution progress to enable prioritization and clear decision-making • Acquire the system Architecture and be part of the leading technical FE forum

Description NextSilicon is reimagining high-performance computing (HPC & AI). Our accelerated compute solutions leverage intelligent adaptive algorithms to vastly accelerate supercomputers, driving them forward into a new generation. We have developed a novel software-defined hardware architecture that is achieving significant advancements in both the HPC and AI domains. At NextSilicon, everything we do is guided by three core values: • Professionalism: We strive for exceptional results through professionalism and unwavering dedication to quality and performance. • Unity: Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard. • Impact: We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide. • NextSilicon is looking for a talented and experienced Logic Design Group Lead to drive and help our group to get to the next era of computer architecture. In this position, you will lead the architecture of NextSilicon’s future chips, driving system-level understanding and the overall architectural flow. You will manage managers and technical leads while remaining highly hands-on, taking an active role in architectural decisions and technical execution across the system. Requirements • B.Sc. in Electrical Engineering or Computer Science • 8+ years of digital design experience with complex blocks • 5+ years as a design team leader • Ability to transform requirements into specification documents • Proven record in high-speed and low-power design • Experience in front-end tools and analysis: CDC, LINT, power, simulation • Experience in network design or compute is an advantage Responsibilities • Be accountable for your group's milestones & timelines • Leading your Group Architecture and developing their abilities • Technology expert, building a knowledge base for the group • Work with various teams to drive execution (SW, Architecture, verification, BE, etc) • Devise execution indicators, monitor and report execution progress to enable prioritization and clear decision-making • Acquire the system Architecture and be part of the leading technical FE forum

Overview Microsoft is building the fastest and most reliable networks for AI and cloud data centers. Microsoft Azure is one of the largest public cloud platforms worldwide, providing a great channel for product impact that touches the lives of millions of users daily. Microsoft’s partnership with world leaders in AI technology provides unparalleled opportunities for innovation at the cutting edge of high-performance computing and networking. Our team has delivered Azure Boost to production through 2 generations and we are now looking for talented hardware design engineers to join our team, developing Azure’s next generation networking ASICs.  Microsoft’s innovative approach for hardware/software co-design leverages custom-designed hardware to offload and accelerate many types of computations and functions of the Azure network. Our vertical work environment offers an unparalleled opportunity to define end-to-end features, implement & test them, participate in their deployment in the cloud, and see your work used on a global scale! Come join us and be challenged daily as you build advanced hardware/software acceleration solutions for some of the world’s largest datacenter networks and AI supercomputers. This is a great opportunity to join a team that has built some of the largest scale cloud systems ever deployed and learn from the very best. Responsibilities • Own and lead the development of a complicated hardware unit in a cloud network device, with deep understanding of its architecture, design and interaction with software. • Design and implement RTL in System Verilog, based on deep understanding of customer requirements, system architecture, and hardware design principles. • Test and debug your designs in simulation and on hardware-based platforms, to reach cloud-scale quality. • Work with software teams on development of drivers and applications. • Deliver the product into cloud production environments and support it through its lifetime. Qualifications • 5+ years of experience in ASIC design • BSc/MSc in Electrical or Computer Engineering, from a major university  Other Requirements: • A versatile can-do, problem-solving attitude, and desire to handle a wide array of challenges.  • Proven analytical, problem-solving, and debugging skills. • Proven communication skills in English #azurecorejobs #azurehardwarejobsil This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Description Chips Talk, We Listen proteanTecs is a game-changing startup that's giving advanced electronics the power to report on their own health. In a digital world built for autonomous driving, cloud computing, and AI, we depend on computing systems daily. But how can we guarantee their safety, reliability and functionality? proteanTecs is the first-ever company to provide visibility into next-gen chips while they are operating, based on the power of on-chip monitoring, machine learning, and data analytics. Here at proteanTecs, you'll be part of a team that's unlocking deep insights to make electronics more reliable, efficient, and high-quality. We're trusted by industry leaders in data centers, automotive, communications, and consumer devices – we work with the world's largest and most notable companies in tech. Why proteanTecs is a great place to work: • Fast-paced and impactful: We're a mission-driven startup, so you'll tackle new challenges daily, wear many hats, and see your work directly influence the future of electronics. • Supportive company culture: Learn from the best. Our 200+ team members are experts in their field with a proven track record of success, and they're committed to fostering a collaborative and supportive work environment. • International presence: We're a multinational company with a diverse team across multiple locations around the globe. You'll collaborate on projects with international impact, gaining a global perspective of the tech industry. • Work with industry leaders: Our solutions are used by the biggest names in tech. You'll be part of the team creating the next generation of groundbreaking products. • Cutting-edge playground: We use the latest machine learning, platforms, and tools to push boundaries and achieve breakthroughs. • Real-world impact: Our work keeps data centers, cars, and other critical systems running smoothly. Your work will directly contribute to safer, more reliable electronics. • We are here for the win: Backed by industry veterans and leading investors, we offer a stable and secure work environment with plenty of room for growth. We are looking for a Seinor Logic Design Engineer to join the ride as we spearhead the next revolution in electronics!. Our Logic Design team builds the on-chip monitoring IP at the heart of the proteanTecs product — digital blocks that ship inside some of the most advanced chips in the industry. We’re growing the team and looking for a Logic Design Engineer to take ownership of that logic, working alongside circuit, verification, physical design, EDA, and AE engineers. A strong fit if you enjoy hard digital design problems in a collaborative, technically demanding environment. Requirements • B.Sc. or M.Sc. in Electrical or Computer Engineering • 5+ years as a VLSI front-end engineer (logic/ASIC/chip design) or in a similar domain • Strong background in RTL design, handoff methodologies, and signoff tools (Lint, CDC, RDC) • Close familiarity with python, Git, Unix-like environment - an advantage • Experience with low-power design techniques (clock gating, power domains, DVFS) - an advantage • Knowledge of DFT design and flows - an advantage Personal skills: • Self-driven — takes a task from definition to signoff, pulling in whoever is needed along the way • Detail-oriented, with a sharp eye for issues others miss • A clear communicator who can convey technical tradeoffs to cross-functional teams • Curious about new design techniques and methodologies Responsibilities • Define and implement digital logic micro-architecture — in plain English, diagrams, and SystemVerilog • Verify design quality against industry standards using static analysis tools (Lint, CDC, RDC) • Work with Circuit Engineers to turn low-level circuit designs into the well-behaved, insightful agents at the core of the proteanTecs solution • Work with Verification Engineers to simulate and debug the digital logic • Work with Physical Design Engineers to ensure correct implementation of proteanTecs’ special circuits

At Johnson & Johnson, we believe health is everything. Our strength in healthcare innovation empowers us to build a world where complex diseases are prevented, treated, and cured, where treatments are smarter and less invasive, and solutions are personal. Through our expertise in Innovative Medicine and MedTech, we are uniquely positioned to innovate across the full spectrum of healthcare solutions today to deliver the breakthroughs of tomorrow, and profoundly impact health for humanity. Learn more at jnj.com. As guided by Our Credo, Johnson & Johnson is responsible to our employees who work with us throughout the world. We provide an inclusive work environment where each person is considered as an individual. At Johnson & Johnson, we respect the diversity and dignity of our employees and recognize their merit. Job Function: R&D Product Development Job Sub Function: R&D Electrical/Mechatronic Engineering Job Category: Scientific/Technology All Job Posting Locations: Yokneam, Haifa District, Israel Job Description: About Johnson & Johnson MedTech Cardiovascular: Fueled by innovation at the intersection of biology and technology, we’re developing the next generation of smarter, less invasive, more personalized treatments. Are you passionate about improving and expanding the possibilities of Cardiovascular? Ready to join a team that’s reimagining how we heal? Our Cardiovascular team develops leading solutions for heart recovery, electrophysiology, and stroke. You will join a proud heritage of continually elevating standards of care for stroke, heart failure and atrial fibrillation (AFib) patients. Your unique talents will help patients on their journey to wellness. Learn more at https://www.jnj.com/medtech We are searching for the best talent for a Logic Designer and FPGA Tech Lead role, to join our team located in Yokneam, Israel. Purpose: We are seeking an experienced Logic Designer and FPGA Technical Lead to join out FPGA team and to provide hands-on technical and architectural leadership for FPGA development in advanced electrophysiology medical systems. This is a strategic individual-contributor role with direct influence on product architecture, technical decisions, delivery, quality, and safety. Your work will contribute to innovative technologies that improve and protect the health of patients worldwide. You will combine deep expertise in logic design, FPGA architecture, and RTL development with multidisciplinary collaboration across hardware, software, systems, algorithms, quality, and regulatory functions to deliver robust FPGA solutions in a regulated environment. Key Responsibilities • Define and own FPGA architectures and detailed design solutions for complex, real-time medical systems. • Lead FPGA development activities end to end, from requirements analysis and architecture through RTL implementation, integration, verification, hardware bring-up, and delivery. • Design, implement, and review high-quality RTL using Verilog and SystemVerilog. • Translate system requirements, communication interfaces, and signal-processing algorithms into efficient FPGA implementations. • Provide technical guidance, conduct design and code reviews, establish engineering best practices, and mentor FPGA engineers. • Drive synthesis, placement and routing, Static Timing Analysis, timing closure, clock-domain crossing analysis, and optimization for performance, power, and resource utilization. • Lead root-cause analysis and resolution of FPGA, board-level, and system-integration issues using simulation and laboratory debugging tools. • Collaborate with hardware, software, systems, algorithms, quality, and regulatory teams to ensure seamless integration and compliance with medical-device development processes. • Maintain clear architecture, interface, verification, implementation, and timing-analysis documentation. Qualifications and Requirements • Bachelor's degree or higher in Electrical Engineering or Computer Engineering. • At least six years of hands-on experience in logic design and FPGA/RTL development, including experience leading complex FPGA designs or providing technical mentorship. • Proven ability to define FPGA architecture and lead development from concept through integration and verification. • Advanced proficiency in Verilog and SystemVerilog. • Hands-on experience with synthesis and implementation tools such as Vivado and Quartus. • Deep understanding of Static Timing Analysis, XDC/SDC constraints, clock-domain crossing, reset design, and low-skew clocking. • Experience with high-speed interfaces and communication protocols such as PCIe, SerDes, I2C, and SPI. • Knowledge of signal-processing algorithms and their implementation in FPGA. • Hands-on hardware bring-up and debugging experience using oscilloscopes, logic analyzers, protocol analyzers, JTAG, and BERT. • Ability to read electrical schematics and a basic understanding of signal integrity, power integrity, power distribution, and thermal requirements. • Strong technical leadership, communication, problem-solving, and cross-functional collaboration skills. • Experience in a regulated medical-device environment is an advantage. • Familiarity with Artix-7 and Kintex UltraScale+ devices is an advantage. #LI-AB6 Required Skills: Preferred Skills: Coaching, Consulting, Critical Thinking, Design Mindset, Design Thinking, Feasibility Studies, Organizing, Problem Solving, Product Knowledge, Program Management, Project Reporting, Quality Focus, Research and Development, Robotic Automation, SAP Product Lifecycle Management, Smart Systems, Technical Research

At Johnson & Johnson, we believe health is everything. Our strength in healthcare innovation empowers us to build a world where complex diseases are prevented, treated, and cured, where treatments are smarter and less invasive, and solutions are personal. Through our expertise in Innovative Medicine and MedTech, we are uniquely positioned to innovate across the full spectrum of healthcare solutions today to deliver the breakthroughs of tomorrow, and profoundly impact health for humanity. Learn more at jnj.com. As guided by Our Credo, Johnson & Johnson is responsible to our employees who work with us throughout the world. We provide an inclusive work environment where each person is considered as an individual. At Johnson & Johnson, we respect the diversity and dignity of our employees and recognize their merit. Job Function: R&D Product Development Job Sub Function: R&D Electrical/Mechatronic Engineering Job Category: People Leader All Job Posting Locations: Yokneam, Haifa District, Israel Job Description: About Johnson & Johnson MedTech Cardiovascular: Fueled by innovation at the intersection of biology and technology, we’re developing the next generation of smarter, less invasive, more personalized treatments. Are you passionate about improving and expanding the possibilities of Cardiovascular? Ready to join a team that’s reimagining how we heal? Our Cardiovascular team develops leading solutions for heart recovery, electrophysiology, and stroke. You will join a proud heritage of continually elevating standards of care for stroke, heart failure and atrial fibrillation (AFib) patients. Your unique talents will help patients on their journey to wellness. Learn more at https://www.jnj.com/medtech We are searching for the best talent for a Logic Designer and FPGA Team Leader role, to join our team located in Yokneam, Israel. Purpose: We are seeking an experienced Logic Designer and FPGA Team Leader to lead and grow the FPGA engineering group developing life‑saving medical systems. This is a key value, strategic role with direct influence on product architecture, delivery, and safety — your work will help improve and protect the health of millions of patients worldwide. You will combine deep technical expertise in Logic Designer and FPGA/RTL design with strong leadership and cross‑functional collaboration to deliver robust, high‑quality FPGA solutions in a regulated environment. Reports to Director of Hardware Engineering and key member of architecture design for the product. Qualifications and Requirements: • Bachelor's degree or higher in Electrical Engineering or Computer Engineering • Proven experience of at least six years in Logic Designer and FPGA/RTL development and more than two years in team management • Ability to design FPGA architecture • Proficiency in Verilog and SystemVerilog • Experience in synthesis and implementation using tools such as Vivado and Quartus • Deep understanding of Static Timing Analysis, constraints (XDC/SDC), and low‑skew clocking • Hands‑on experience in hardware brings‑up: oscilloscopes, logic analyzers, protocol analyzers, JTAG, BERT • Familiarity with PCIe and SerDes protocols and experience with signal‑processing algorithms • Ability to read electrical schematics and a basic understanding of SI/PI and power/cooling requirements • Advantage: familiarity with Artix‑7 and Kintex UltraScale+ devices • Ability to lead and grow a team of FPGA designers • Proven ability for managing cross platforms and technologies #LI-AB6 #LI-Hybrid Required Skills: Preferred Skills: Business Behavior, Consulting, Critical Thinking, Design Mindset, Design Thinking, Developing Others, Electrical Engineering, Feasibility Studies, Inclusive Leadership, Leadership, Mechanical Engineering, Quality Focus, Research and Development, Robotic Automation, SAP Product Lifecycle Management, Science, Technology, Engineering, and Math (STEM) Application, Smart Systems, Technical Research

Job Details: Job Description: Altera is seeking a highly motivated and skilled Logic Designer to contribute to the development of cutting-edge programmable logic devices. This role involves designing, verifying, and implementing complex digital logic for our next-generation FPGA products. Job Title: Senior Logic/DSP Design Engineer – Mixed Signal Location: Israel Department: Analog Mixed Signal Serdes (AMS) About the Role We are seeking a Senior Logic/DSP Design Engineer to develop digital logic and DSP algorithms supporting mixed-signal IP blocks (e.g., high-speed SerDes, ADC/DAC digital, calibration engines, and control logic). This role bridges the digital and analog domains — translating system-level and DSP algorithms into synthesizable RTL, and working closely with analog/mixed-signal architects to close the loop on calibration, equalization, and adaptive control. Key Responsibilities • Micro-Architect Design and implement digital logic (RTL) for mixed-signal subsystems — calibration state machines, digital filters, adaptive equalization, clock/data recovery digital loops, etc. • Collaborate with analog design teams to define digital-analog interfaces, calibration flows, and control logic. • Perform RTL-to-gate synthesis, timing closure, and low-power design techniques for mixed-signal digital blocks. • Build and maintain block level verification environments (Verilog) for digital logic tied to analog behavior (mixed-signal verification, AMS co-simulation). • Support silicon bring-up and debug — correlating digital logic behavior with analog measurements in the lab. • Document architecture, algorithms, and design decisions; participate in design and code reviews. • Mentor junior engineers on digital design practices within a mixed-signal flow. Qualifications: • BSC/MSC in Electrical Engineering. • 7+ years of experience in digital logic design, with exposure to mixed-signal or DSP projects. • Strong RTL design skills (Verilog) and synthesis flow experience • Solid understanding of DSP fundamentals (filtering, sampling, quantization, timing recovery). • Familiarity with mixed-signal verification methodologies (AMS simulation, Verilog-AMS, real number modeling). Preferred Qualifications • Experience with high-speed SerDes, PCIe, DisplayPort, Ethernet or similar interface standards. • Exposure to calibration/adaptation algorithms for ADCs, DACs, or equalizers. • Familiarity with low-power design techniques and static timing analysis (STA). • Experience working directly with analog designers on digital-analog co-design. Job Type: Regular Shift: Shift 1 (Israel) Primary Location: Haifa, Israel Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Job Description Meet the Team Join the Cisco Silicon One Front-End Design team, at the core of Cisco’s silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation. We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of what’s possible. Cisco Silicon One™ is transforming the industry with a unified, programmable architecture powering Cisco’s future routing portfolio and shaping the Internet for decades to come. Your Impact · Write and review micro-architecture specifications · Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements · Contribute to full chip integration, timing methodology, and analysis · Collaborate with verification engineers to resolve bugs and achieve coverage closure · Work with the physical design team to close timing and PnR issues · Support design methodology evolution and best practices · Perform debug, root-cause analysis, and post-silicon validation in the lab Minimum Qualifications · B.Sc./M.Sc. in Electrical Engineering from a top university · 6+ years of experience in a relevant field · RTL design experience · Familiarity with UVM and functional verification methodologies Preferred Qualifications · Experience with MATLAB simulations and bit-exact modeling environments · Familiarity with mixed-signal systems and environments · Knowledge and hands-on experience with Clock Domain Crossing (CDC) Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

At Johnson & Johnson, we believe health is everything. Our strength in healthcare innovation empowers us to build a world where complex diseases are prevented, treated, and cured, where treatments are smarter and less invasive, and solutions are personal. Through our expertise in Innovative Medicine and MedTech, we are uniquely positioned to innovate across the full spectrum of healthcare solutions today to deliver the breakthroughs of tomorrow, and profoundly impact health for humanity. Learn more at jnj.com. As guided by Our Credo, Johnson & Johnson is responsible to our employees who work with us throughout the world. We provide an inclusive work environment where each person is considered as an individual. At Johnson & Johnson, we respect the diversity and dignity of our employees and recognize their merit. Job Function: R&D Product Development Job Sub Function: R&D Electrical/Mechatronic Engineering Job Category: People Leader All Job Posting Locations: Yokneam, Haifa District, Israel Job Description: About Johnson & Johnson MedTech Cardiovascular: Fueled by innovation at the intersection of biology and technology, we’re developing the next generation of smarter, less invasive, more personalized treatments. Are you passionate about improving and expanding the possibilities of Cardiovascular? Ready to join a team that’s reimagining how we heal? Our Cardiovascular team develops leading solutions for heart recovery, electrophysiology, and stroke. You will join a proud heritage of continually elevating standards of care for stroke, heart failure and atrial fibrillation (AFib) patients. Your unique talents will help patients on their journey to wellness. Learn more at https://www.jnj.com/medtech We are searching for the best talent for a Logic Designer and FPGA Team Leader role, to join our team located in Yokneam, Israel. Purpose: We are seeking an experienced Logic Designer and FPGA Team Leader to lead and grow the FPGA engineering group developing life‑saving medical systems. This is a key value, strategic role with direct influence on product architecture, delivery, and safety — your work will help improve and protect the health of millions of patients worldwide. You will combine deep technical expertise in Logic Designer and FPGA/RTL design with strong leadership and cross‑functional collaboration to deliver robust, high‑quality FPGA solutions in a regulated environment. Reports to Director of Hardware Engineering and key member of architecture design for the product. Qualifications and Requirements: • Bachelor's degree or higher in Electrical Engineering or Computer Engineering • Proven experience of at least six years in Logic Designer and FPGA/RTL development and more than two years in team management • Ability to design FPGA architecture • Proficiency in Verilog and SystemVerilog • Experience in synthesis and implementation using tools such as Vivado and Quartus • Deep understanding of Static Timing Analysis, constraints (XDC/SDC), and low‑skew clocking • Hands‑on experience in hardware brings‑up: oscilloscopes, logic analyzers, protocol analyzers, JTAG, BERT • Familiarity with PCIe and SerDes protocols and experience with signal‑processing algorithms • Ability to read electrical schematics and a basic understanding of SI/PI and power/cooling requirements • Advantage: familiarity with Artix‑7 and Kintex UltraScale+ devices • Ability to lead and grow a team of FPGA designers • Proven ability for managing cross platforms and technologies #LI-AB6 #LI-Hybrid Required Skills: Preferred Skills: Business Behavior, Consulting, Critical Thinking, Design Mindset, Design Thinking, Developing Others, Electrical Engineering, Feasibility Studies, Inclusive Leadership, Leadership, Mechanical Engineering, Quality Focus, Research and Development, Robotic Automation, SAP Product Lifecycle Management, Science, Technology, Engineering, and Math (STEM) Application, Smart Systems, Technical Research

At Johnson & Johnson, we believe health is everything. Our strength in healthcare innovation empowers us to build a world where complex diseases are prevented, treated, and cured, where treatments are smarter and less invasive, and solutions are personal. Through our expertise in Innovative Medicine and MedTech, we are uniquely positioned to innovate across the full spectrum of healthcare solutions today to deliver the breakthroughs of tomorrow, and profoundly impact health for humanity. Learn more at jnj.com. As guided by Our Credo, Johnson & Johnson is responsible to our employees who work with us throughout the world. We provide an inclusive work environment where each person is considered as an individual. At Johnson & Johnson, we respect the diversity and dignity of our employees and recognize their merit. Job Function: R&D Product Development Job Sub Function: R&D Electrical/Mechatronic Engineering Job Category: Scientific/Technology All Job Posting Locations: Yokneam, Haifa District, Israel Job Description: About Johnson & Johnson MedTech Cardiovascular: Fueled by innovation at the intersection of biology and technology, we’re developing the next generation of smarter, less invasive, more personalized treatments. Are you passionate about improving and expanding the possibilities of Cardiovascular? Ready to join a team that’s reimagining how we heal? Our Cardiovascular team develops leading solutions for heart recovery, electrophysiology, and stroke. You will join a proud heritage of continually elevating standards of care for stroke, heart failure and atrial fibrillation (AFib) patients. Your unique talents will help patients on their journey to wellness. Learn more at https://www.jnj.com/medtech We are searching for the best talent for a Logic Designer and FPGA Tech Lead role, to join our team located in Yokneam, Israel. Purpose: We are seeking an experienced Logic Designer and FPGA Technical Lead to join out FPGA team and to provide hands-on technical and architectural leadership for FPGA development in advanced electrophysiology medical systems. This is a strategic individual-contributor role with direct influence on product architecture, technical decisions, delivery, quality, and safety. Your work will contribute to innovative technologies that improve and protect the health of patients worldwide. You will combine deep expertise in logic design, FPGA architecture, and RTL development with multidisciplinary collaboration across hardware, software, systems, algorithms, quality, and regulatory functions to deliver robust FPGA solutions in a regulated environment. Key Responsibilities • Define and own FPGA architectures and detailed design solutions for complex, real-time medical systems. • Lead FPGA development activities end to end, from requirements analysis and architecture through RTL implementation, integration, verification, hardware bring-up, and delivery. • Design, implement, and review high-quality RTL using Verilog and SystemVerilog. • Translate system requirements, communication interfaces, and signal-processing algorithms into efficient FPGA implementations. • Provide technical guidance, conduct design and code reviews, establish engineering best practices, and mentor FPGA engineers. • Drive synthesis, placement and routing, Static Timing Analysis, timing closure, clock-domain crossing analysis, and optimization for performance, power, and resource utilization. • Lead root-cause analysis and resolution of FPGA, board-level, and system-integration issues using simulation and laboratory debugging tools. • Collaborate with hardware, software, systems, algorithms, quality, and regulatory teams to ensure seamless integration and compliance with medical-device development processes. • Maintain clear architecture, interface, verification, implementation, and timing-analysis documentation. Qualifications and Requirements • Bachelor's degree or higher in Electrical Engineering or Computer Engineering. • At least six years of hands-on experience in logic design and FPGA/RTL development, including experience leading complex FPGA designs or providing technical mentorship. • Proven ability to define FPGA architecture and lead development from concept through integration and verification. • Advanced proficiency in Verilog and SystemVerilog. • Hands-on experience with synthesis and implementation tools such as Vivado and Quartus. • Deep understanding of Static Timing Analysis, XDC/SDC constraints, clock-domain crossing, reset design, and low-skew clocking. • Experience with high-speed interfaces and communication protocols such as PCIe, SerDes, I2C, and SPI. • Knowledge of signal-processing algorithms and their implementation in FPGA. • Hands-on hardware bring-up and debugging experience using oscilloscopes, logic analyzers, protocol analyzers, JTAG, and BERT. • Ability to read electrical schematics and a basic understanding of signal integrity, power integrity, power distribution, and thermal requirements. • Strong technical leadership, communication, problem-solving, and cross-functional collaboration skills. • Experience in a regulated medical-device environment is an advantage. • Familiarity with Artix-7 and Kintex UltraScale+ devices is an advantage. #LI-AB6 Required Skills: Preferred Skills: Coaching, Consulting, Critical Thinking, Design Mindset, Design Thinking, Feasibility Studies, Organizing, Problem Solving, Product Knowledge, Program Management, Project Reporting, Quality Focus, Research and Development, Robotic Automation, SAP Product Lifecycle Management, Smart Systems, Technical Research

The NVIDIA CPU team is a world-class, global organization united by a mission to push the boundaries of what’s possible and shape the future of computing. We are looking for a talented, fast-learning and highly motivated Senior Logic Design Engineer to join our team. As part of the core design team, you’ll take ownership of parts of the design and work closely with architecture, verification, and physical design teams, contributing to a fast-moving, technology-focused environment and helping shape future products. What you'll be doing: • As part of the CPU core team, you’ll take ownership of a unit. • Contributing to the micro-architecture, writing RTL and documentation. • Working closely with verification and implementation teams to meet timing, area, performance, and power goals. What we need to see: • A Bachelor’s Degree in Electrical Engineering, Computer Engineering or Computer Science, or equivalent experience • 8+ years in processor or high-performance semiconductor design • Strong RTL expertise and solid computer architecture background • Strong communication and interpersonal skills. • Proven ownership and technical leadership of complex design blocks • Track record of driving design and verification initiatives (e.g., uArch, methodology, efficiency) Ways to stand out from the crowd: • A strong background in computer architecture is highly desirable. • Experience with AI-assisted development tools (e.g., Cursor, Claude Code, or similar) is a plus NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power-efficient chips in their class? If so, come join our CPU design team, we want to hear from you!

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The NVIDIA System-On-Chip (SOC) group is looking for a strong RTL Design Engineer to own the SOC clocking logic for our next-generation networking chips. Clocks are the backbone of the SOC. In this role you will own the clock generation, distribution, and control logic for the entire chip — PLL and reference clock integration, clock muxing and dividers, glitchless switching, clock gating, reset synchronization, and the clock domain crossing infrastructure that every unit on the die depends on. This is an RTL design role, not a circuit or transistor-level design role. You will translate micro-architecture specifications into high-quality synthesizable RTL, and drive that RTL through to silicon in close partnership with the micro-architecture, Design Verification, and Physical Design (backend) teams. You will also interact with CAD, Package Design, Software, and DFT teams. What you'll be doing: • Owning the SOC clocking logic end to end: writing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization, from micro-architecture specification through tape-out • Defining and implementing the SOC clock and reset architecture together with the micro-architecture team — collecting clocking requirements from every unit on the chip and turning them into a coherent, verifiable design • Owning clock domain crossing infrastructure and CDC closure across the SOC • Partnering with the micro-architecture team to review specifications, close on design intent, and provide feedback on implementation cost, timing, area, and power • Working hand-in-hand with the Physical Design (backend) team on clock tree implementation and constraints, partitioning, floorplan and timing feedback, trial synthesis, congestion and timing convergence, and physical design readiness • Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows • Driving design quality: lint, CDC/RDC, formal checks, synthesis QoR, connectivity and structural checks • Supporting SOC-level chip build and assembly, and developing/deploying automation flows that make RTL integration and design quality checking repeatable and scalable • Supporting emulation, firmware, and post-silicon bring-up customers of your design What we need to see: • B.Sc./M.Sc. in Electrical Engineering or Computer Engineering • 3+ years of relevant experience in RTL/logic design • Solid hands-on RTL design skills in Verilog/SystemVerilog, with a good understanding of synthesis, timing, and how RTL choices affect the physical implementation • Experience taking a design from micro-architecture specification through verification and physical implementation • Solid understanding of clocking and reset concepts: clock gating, clock muxing and dividers, glitchless clock switching, reset synchronization, and clock domain crossing • Familiarity with design quality tooling (lint, CDC/RDC, formal, synthesis) • Great teammate with strong communication skills across micro-architecture, DV, and backend teams Ways to stand out from the crowd: • Passion for quality, and a track record of clean deliveries to physical design, DV, emulation, firmware, and other downstream customers • Prior ownership of SOC-level clocking or reset architecture on a taped-out chip • Experience with PLL/clock generator integration and clock tree constraint development with backend teams At NVIDIA, you will be immersed in a diverse and encouraging environment where everyone is encouraged to do their best work. Join us and see how you can make a lasting impact on the world. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law

The NVIDIA CPU team is a world-class, global organization united by a mission to push the boundaries of what’s possible and shape the future of computing. We are looking for a talented, fast-learning and highly motivated Logic Design Engineer to join our team. As part of the core design team, you’ll take ownership of parts of the design and work closely with architecture, verification, and physical design teams, contributing to a fast-moving, technology-focused environment and helping shape future products. What you'll be doing: • As part of the CPU core team, you’ll take ownership of a unit. • Contributing to the micro-architecture, writing RTL and documentation. • Working closely with verification and implementation teams to meet timing, area, performance, and power goals. What we need to see: • A Bachelor’s Degree in Electrical Engineering, Computer Engineering or Computer Science, or equivalent experience. • 2+ years of experience in processor or other related high-performance semiconductor designs. • Hardware description language expertise required • Strong communication and interpersonal skills. Ways to stand out from the crowd: • A strong background in computer architecture is highly desirable. • Experience with AI-assisted development tools (e.g., Cursor, Claude Code, or similar) is a plus. NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power-efficient chips in their class? If so, come join our CPU design team, we want to hear from you!

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The NVIDIA System-On-Chip (SOC) group is looking for a Senior RTL Design Engineer to serve as the technical lead for clocks development on our next-generation networking chips. Clocks are the backbone of the SOC. In this role you will lead the development of the chip's clocking logic — PLL and reference clock integration, clock generation, distribution, muxing and dividers, glitchless switching, clock gating, reset synchronization, and the clock domain crossing infrastructure that every unit on the die depends on. This is an RTL design and technical leadership role, not a circuit or transistor-level design role. Working from the clock architecture defined with the architecture and micro-architecture teams, you will lead its implementation in RTL, guide other engineers contributing to it, and drive it through to silicon in close partnership with Design Verification and Physical Design (backend). You will also interact regularly with CAD, Package Design, Software, and DFT teams. What you'll be doing: • Acting as the technical lead for SOC clocks development — leading the implementation of the clocking logic from specification through tape-out and bring-up • Working with the architecture and micro-architecture teams on the SOC clock and reset scheme: collecting clocking requirements from units across the chip, feeding back implementation and timing considerations, and translating the agreed scheme into a verifiable design • Writing and reviewing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization • Leading and mentoring other RTL engineers working on clocking: reviewing designs, setting coding and quality standards, and distributing work across the team • Working hand-in-hand with the Physical Design (backend) team on clock tree implementation, SDC/timing constraints, partitioning, floorplan feedback, trial synthesis, and timing convergence • Partnering with Design Verification on clocking testplans, functional and gate-level debug, and coverage closure • Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows • Representing clocking implementation in cross-functional design reviews with architecture, PD, DV, DFT, and CAD stakeholders What we need to see: • B.Sc./M.Sc. in Electrical Engineering or Computer Engineering • 8+ years of relevant experience in RTL/logic design, with multiple chips taken to tape-out • Demonstrated technical leadership: leading a design area through implementation and tape-out, mentoring engineers, and coordinating across teams • Expert hands-on RTL design skills in Verilog/SystemVerilog, with strong understanding of how RTL choices affect synthesis results, timing, area, and power • Deep understanding of clocking and reset design: clock gating, clock muxing and dividers, glitchless clock switching, reset synchronization, and clock domain crossing • Proficiency with design quality tooling — lint, CDC/RDC, formal verification, synthesis, and static timing analysis (STA) — including the ability to interpret results and drive fixes back into the RTL • Experience taking a design from architecture and micro-architecture specification through verification, physical implementation, and silicon bring-up • Great teammate with strong communication skills across micro-architecture, DV, backend, DFT, and software teams Ways to stand out from the crowd: • Prior hands-on experience with SOC-level clocking or reset logic on a taped-out chip • Experience with PLL/clock generator integration and clock tree constraint development with backend teams • Experience with high-speed networking, interconnect, or fabric designs • Background with low-power design techniques (clock gating, DVFS, power domains, UPF) • Experience building automation for RTL integration, chip assembly, or design quality flows At NVIDIA, you will be immersed in a diverse and encouraging environment where everyone is encouraged to do their best work. Join us and see how you can make a lasting impact on the world. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Description Quantum Machines is a global leader in control systems for quantum computing, a field on the verge of exponential growth, bringing about opportunities like those made possible with the invention of classical computing 50 years ago. At QM, we provide the world’s most leading researchers and organizations with the critical tools they need to develop useful quantum computers. QM’s hardware and software represent a new paradigm for controlling quantum computers, from a single qubit to hundreds and thousands. We are assembling the strongest team of professionals in the world with the goal of revolutionizing how quantum computers are built and controlled and accelerating their arrival. Quantum Machines is backed by globally recognized venture capital sponsors, including TLV Partners, Battery Ventures, Red Dot Capital Partners, Avigdor Willenz’ investment group, Harel Insurance, and others. We are looking for an excellent design engineer to join our team and build QM's state-of-the-art control and orchestration platform. We are looking for a highly talented and motivated person, who is a real team player, and which can collaborate closely with engineers from other disciplines and quantum physicists Responsibilities: • Designing a configurable and very low-latency challenging RTL • Bringing the state-of-the-art FPGA to its limits with regards to logic & timing optimization • End2end ownership of the entire coding process (Arch->uArch->Design->Implementation) • Learning system and SW requirements for proper implementation of HW-SW interface Requirements: • BSc in electrical/computer engineering or relevant military background • At least 4 years of experience • Proven track record in RTL coding with System Verilog • Experience with System Verilog • VCS, Vivado - Advantage

Job Details: Job Description: As part of Intel's Core Engineering Group, we develop Intel's main and most valuable and complex IP: the Intel Performance Core. The Core is the central component of many Intel products, including desktops, notebooks, servers, cloud CPUs, and emerging AI platforms. Our Core technology powers hundreds of millions of products every year and drives innovations across cloud computing, AI, networking, communications, and consumer markets. The team is responsible for developing and managing critical mechanisms at the heart of Intel's next-generation Performance Core architecture. Our work has a direct impact on performance, power efficiency, scalability, and product competitiveness across Intel's CPU portfolio. About the Job We are looking for an experienced Logic RTL Design Engineer to join the Out-of-Order team. In this role: • you will define micro-architecture, develop RTL, and drive the implementation of complex allocation and resource management mechanisms in Intel's high-performance CPU cores. • You will own features from architecture exploration through RTL development, validation support, debug, and tape-in readiness. • You will lead significant design efforts, drive micro-architectural tradeoff discussions, and collaborate closely with architecture, verification, physical design, power-performance, and post-silicon teams. This is a unique opportunity to influence core technologies that directly impact CPU performance, power efficiency, and scalability while contributing to future generations of Intel Core products. Qualifications: • B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field. • At least 5 years of experience in RTL logic design and development using SystemVerilog. • Strong understanding of computer architecture, micro-architecture, and digital design principles. • Experience defining and implementing complex micro-architectural features. • Strong debugging and problem-solving skills. • Ability to independently drive features from definition through implementation and validation. • Excellent communication and teamwork skills. • Experience collaborating with architecture, validation, design, and post-silicon teams. • Nice to Have • Experience with design partitioning and micro-architectural tradeoff analysis. • Experience developing functional validation and coverage plans together with verification teams. • Experience working on high-performance CPU or cache/memory subsystem designs. • Experience with timing closure, power optimization, and performance analysis. • Knowledge of power-aware RTL coding methodologies and power debugging techniques. • Familiarity with advanced design methodologies, scripting, and automation. • Experience working with geographically distributed and cross-functional engineering teams Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Haifa Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *