Logic Design Engineer jobs in Tel Aviv-Yafo

Job Description Meet the Team Join the Cisco Silicon One Front-End Design team, at the core of Cisco’s silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation. We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of what’s possible. Cisco Silicon One™ is transforming the industry with a unified, programmable architecture powering Cisco’s future routing portfolio and shaping the Internet for decades to come. Your Impact · Write and review micro-architecture specifications · Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements · Contribute to full chip integration, timing methodology, and analysis · Collaborate with verification engineers to resolve bugs and achieve coverage closure · Work with the physical design team to close timing and PnR issues · Support design methodology evolution and best practices · Perform debug, root-cause analysis, and post-silicon validation in the lab Minimum Qualifications · B.Sc./M.Sc. in Electrical Engineering from a top university · 6+ years of experience in a relevant field · RTL design experience · Familiarity with UVM and functional verification methodologies Preferred Qualifications · Experience with MATLAB simulations and bit-exact modeling environments · Familiarity with mixed-signal systems and environments · Knowledge and hands-on experience with Clock Domain Crossing (CDC) Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The NVIDIA System-On-Chip (SOC) group is looking for a Senior RTL Design Engineer to serve as the technical lead for clocks development on our next-generation networking chips. Clocks are the backbone of the SOC. In this role you will lead the development of the chip's clocking logic — PLL and reference clock integration, clock generation, distribution, muxing and dividers, glitchless switching, clock gating, reset synchronization, and the clock domain crossing infrastructure that every unit on the die depends on. This is an RTL design and technical leadership role, not a circuit or transistor-level design role. Working from the clock architecture defined with the architecture and micro-architecture teams, you will lead its implementation in RTL, guide other engineers contributing to it, and drive it through to silicon in close partnership with Design Verification and Physical Design (backend). You will also interact regularly with CAD, Package Design, Software, and DFT teams. What you'll be doing: • Acting as the technical lead for SOC clocks development — leading the implementation of the clocking logic from specification through tape-out and bring-up • Working with the architecture and micro-architecture teams on the SOC clock and reset scheme: collecting clocking requirements from units across the chip, feeding back implementation and timing considerations, and translating the agreed scheme into a verifiable design • Writing and reviewing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization • Leading and mentoring other RTL engineers working on clocking: reviewing designs, setting coding and quality standards, and distributing work across the team • Working hand-in-hand with the Physical Design (backend) team on clock tree implementation, SDC/timing constraints, partitioning, floorplan feedback, trial synthesis, and timing convergence • Partnering with Design Verification on clocking testplans, functional and gate-level debug, and coverage closure • Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows • Representing clocking implementation in cross-functional design reviews with architecture, PD, DV, DFT, and CAD stakeholders What we need to see: • B.Sc./M.Sc. in Electrical Engineering or Computer Engineering • 8+ years of relevant experience in RTL/logic design, with multiple chips taken to tape-out • Demonstrated technical leadership: leading a design area through implementation and tape-out, mentoring engineers, and coordinating across teams • Expert hands-on RTL design skills in Verilog/SystemVerilog, with strong understanding of how RTL choices affect synthesis results, timing, area, and power • Deep understanding of clocking and reset design: clock gating, clock muxing and dividers, glitchless clock switching, reset synchronization, and clock domain crossing • Proficiency with design quality tooling — lint, CDC/RDC, formal verification, synthesis, and static timing analysis (STA) — including the ability to interpret results and drive fixes back into the RTL • Experience taking a design from architecture and micro-architecture specification through verification, physical implementation, and silicon bring-up • Great teammate with strong communication skills across micro-architecture, DV, backend, DFT, and software teams Ways to stand out from the crowd: • Prior hands-on experience with SOC-level clocking or reset logic on a taped-out chip • Experience with PLL/clock generator integration and clock tree constraint development with backend teams • Experience with high-speed networking, interconnect, or fabric designs • Background with low-power design techniques (clock gating, DVFS, power domains, UPF) • Experience building automation for RTL integration, chip assembly, or design quality flows At NVIDIA, you will be immersed in a diverse and encouraging environment where everyone is encouraged to do their best work. Join us and see how you can make a lasting impact on the world. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The NVIDIA System-On-Chip (SOC) group is looking for a strong RTL Design Engineer to own the SOC clocking logic for our next-generation networking chips. Clocks are the backbone of the SOC. In this role you will own the clock generation, distribution, and control logic for the entire chip — PLL and reference clock integration, clock muxing and dividers, glitchless switching, clock gating, reset synchronization, and the clock domain crossing infrastructure that every unit on the die depends on. This is an RTL design role, not a circuit or transistor-level design role. You will translate micro-architecture specifications into high-quality synthesizable RTL, and drive that RTL through to silicon in close partnership with the micro-architecture, Design Verification, and Physical Design (backend) teams. You will also interact with CAD, Package Design, Software, and DFT teams. What you'll be doing: • Owning the SOC clocking logic end to end: writing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization, from micro-architecture specification through tape-out • Defining and implementing the SOC clock and reset architecture together with the micro-architecture team — collecting clocking requirements from every unit on the chip and turning them into a coherent, verifiable design • Owning clock domain crossing infrastructure and CDC closure across the SOC • Partnering with the micro-architecture team to review specifications, close on design intent, and provide feedback on implementation cost, timing, area, and power • Working hand-in-hand with the Physical Design (backend) team on clock tree implementation and constraints, partitioning, floorplan and timing feedback, trial synthesis, congestion and timing convergence, and physical design readiness • Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows • Driving design quality: lint, CDC/RDC, formal checks, synthesis QoR, connectivity and structural checks • Supporting SOC-level chip build and assembly, and developing/deploying automation flows that make RTL integration and design quality checking repeatable and scalable • Supporting emulation, firmware, and post-silicon bring-up customers of your design What we need to see: • B.Sc./M.Sc. in Electrical Engineering or Computer Engineering • 3+ years of relevant experience in RTL/logic design • Solid hands-on RTL design skills in Verilog/SystemVerilog, with a good understanding of synthesis, timing, and how RTL choices affect the physical implementation • Experience taking a design from micro-architecture specification through verification and physical implementation • Solid understanding of clocking and reset concepts: clock gating, clock muxing and dividers, glitchless clock switching, reset synchronization, and clock domain crossing • Familiarity with design quality tooling (lint, CDC/RDC, formal, synthesis) • Great teammate with strong communication skills across micro-architecture, DV, and backend teams Ways to stand out from the crowd: • Passion for quality, and a track record of clean deliveries to physical design, DV, emulation, firmware, and other downstream customers • Prior ownership of SOC-level clocking or reset architecture on a taped-out chip • Experience with PLL/clock generator integration and clock tree constraint development with backend teams At NVIDIA, you will be immersed in a diverse and encouraging environment where everyone is encouraged to do their best work. Join us and see how you can make a lasting impact on the world. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law

Description Quantum Machines is a global leader in control systems for quantum computing, a field on the verge of exponential growth, bringing about opportunities like those made possible with the invention of classical computing 50 years ago. At QM, we provide the world’s most leading researchers and organizations with the critical tools they need to develop useful quantum computers. QM’s hardware and software represent a new paradigm for controlling quantum computers, from a single qubit to hundreds and thousands. We are assembling the strongest team of professionals in the world with the goal of revolutionizing how quantum computers are built and controlled and accelerating their arrival. Quantum Machines is backed by globally recognized venture capital sponsors, including TLV Partners, Battery Ventures, Red Dot Capital Partners, Avigdor Willenz’ investment group, Harel Insurance, and others. We are looking for an excellent design engineer to join our team and build QM's state-of-the-art control and orchestration platform. We are looking for a highly talented and motivated person, who is a real team player, and which can collaborate closely with engineers from other disciplines and quantum physicists Responsibilities: • Designing a configurable and very low-latency challenging RTL • Bringing the state-of-the-art FPGA to its limits with regards to logic & timing optimization • End2end ownership of the entire coding process (Arch->uArch->Design->Implementation) • Learning system and SW requirements for proper implementation of HW-SW interface Requirements: • BSc in electrical/computer engineering or relevant military background • At least 4 years of experience • Proven track record in RTL coding with System Verilog • Experience with System Verilog • VCS, Vivado - Advantage