ASIC DFT Engineer jobs in Israel

Description We are looking for a talented and experienced DFT Tech Lead. As a DFT Tech Lead you will work closely with all other design teams – backend, vlsi, verification and analog, fully responsible for defining, implementing, and deploying advanced design-for-test (DFT) methodologies for highly complex digital and mixed-signal chips. You will define silicon test strategies, DFT/DFD architecture, and create DFT and Debug specifications for complex next generation SoCs. Requirements Minimum qualifications: • 8+ Experience in DFT specification definition, architecture, insertion, and analysis in designs • Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG-related issues • Experience in fault modeling Preferred qualifications: • Master's degree in Electrical Engineering. • Experience in IP integration (memories, Test controllers, TAP, MBIST). • Experience using EDA Test tools like Design/Fusion Compiler, DFT Max, SpyGlass, Modus, Tessent, and TestKompress. • Experience and understanding of ASIC DFT, synthesis, simulation and verification flow. • Excellent attention to detail organizational, problem-solving, and communication skills. Responsibilities: • Create SoC DFT strategy and architecture (ATPG/DFT/MBIST) • Work on hierarchical design • Debug all Design Rule checks, apply design fixes to achieve high test quality • Insert all DFT logic - boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks. • Insert and hook up MBIST logic. • Define test plan for special analog IPs and implement. • Document DFT architecture and test sequences, including boot-up sequence associated with test pins.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Staff DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters. As a Staff DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools—you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity. Key Responsibilities • DFT Architecture & Strategy • Own the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support • Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards • ​DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG methodologies • Test Pattern Development & Optimization • Generate and optimize high-quality test and debug patterns for production • Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance • Drive test coverage and quality metrics to meet stringent manufacturing requirements • Cross-Functional Collaboration & Methodology Innovation • Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR • Participate in developing and maintaining cutting-edge DFT implementation flows • Automate and improve methodologies using advanced scripting and tools Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 8+ years of hands-on experience in DFT roles at semiconductor companies • Deep expertise in DFT flows and architectures including JTAG/iJTAG, MBIST, Scan, and ATPG • Proficiency with industry-standard EDA tools from Synopsys (TestMAX) or Mentor (Tessent) • Strong understanding of logic design, verification, debug, and Static Timing Analysis (STA) • Scripting proficiency in Tcl, Perl, Python, or Shell for automation and innovation Preferred Qualifications • Master's degree in Electrical Engineering or related field • Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) and their specific test requirements • Experience in chip bring-up and mass production activities • Background in advanced process technologies (7nm and below) • Excellent communication skills with ability to work effectively in global team environments We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters. As a DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools—you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity. Key Responsibilities • DFT Architecture & Strategy • Be part of the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support • Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards • Design and implement DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG for high-end devices • Test Pattern Development & Optimization • Generate and optimize high-quality test and debug patterns for production • Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance • Drive test coverage and quality metrics to meet stringent manufacturing requirements • Cross-Functional Collaboration & Methodology Innovation • Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR • Participate in developing and maintaining cutting-edge DFT implementation flows • Automate and improve methodologies using advanced scripting and tools Basic Qualifications • Bachelor's degree in Electrical Engineering or related technical field • 4+ years of hands-on experience in DFT roles at semiconductor companies • Experience in DFT flows and architectures including JTAG/iJTAG, MBIST, Scan, and ATPG • Good understanding of logic design, verification, debug, and Static Timing Analysis (STA) • Scripting proficiency in Tcl, Perl, Python, or Shell for automation and innovation Preferred Qualifications • Master's degree in Electrical Engineering or related field • Experience with industry-standard EDA tools from Synopsys (TestMAX) or Siemens (Tessent) • Experience in chip bring-up and mass production activities • Background in advanced process technologies (7nm and below) • Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) and their specific test requirements • Excellent communication skills with ability to work effectively in global team environments We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Principal DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters. As a Principal DFT Engineer, you will provide technical leadership across the full DFT lifecycle—from architecture and specification through implementation, verification, and silicon bring-up. You will define and drive DFT strategy, establish robust methodologies, and lead execution to ensure high test quality and manufacturability. This role requires deep expertise, cross-functional influence, and the ability to drive DFT excellence across projects and teams. This is a critical leadership position with high impact on first-pass silicon success and production quality for next-generation AI connectivity solutions. Key Responsibilities DFT Architecture & Technical Leadership • Define and own DFT architecture for complex SoCs, including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG strategies • Lead DFT planning, specification, and quality tracking across the project lifecycle • Provide technical leadership and drive DFT sign-off readiness to ensure successful tapeout Execution Across the Full Lifecycle • Lead DFT implementation, integration, and verification at block, full-chip and chiplet levels • Own end-to-end DFT activities from specification through silicon bring-up and production support • Ensure high test coverage, robust pattern generation, and alignment with manufacturing requirements Methodology & Cross-Functional Impact • Develop and drive scalable DFT methodologies, flows, and automation frameworks • Collaborate closely with RTL, Physical Design, STA, and Test Engineering teams to ensure design-for-test readiness • Optimize DFT integration across front-end and backend flows to improve quality, PPA, and turnaround time Basic Qualifications • Bachelor’s degree in Electrical Engineering or related technical field (Master’s preferred) • 12+ years of experience in DFT design, implementation, and verification for complex ASIC/SoC designs • Proven experience in leading DFT activities across full chip development cycles • Deep expertise in DFT techniques including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG • Strong understanding of DFT and Physical Design flows, including timing implications and integration challenges • Experience with industry-standard DFT tools (Siemens Tessent, Synopsys TestMAX or equivalent) • Solid experience with DFT verification methodologies and coverage analysis • Strong scripting skills (Tcl, Python, or Perl) for automation and flow development Preferred Qualifications • Experience with advanced process nodes (7nm and below) • Background in high-speed connectivity designs (PCIe, Ethernet, CXL, or similar) • Experience with hierarchical DFT methodologies and large multi-die or chiplet-based systems • Knowledge of silicon bring-up, production test flows, and yield optimization • Familiarity with STA, low-power design, and CDC as it relates to DFT integration • Strong leadership and communication skills, with ability to influence cross-functional teams globally We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Job Details: Job Description: Altera is seeking a skilled DFT Design Engineer to contribute to the design and implementation of Design-for-Test (DFT) solutions for complex integrated circuits, ensuring high test coverage and efficient manufacturing test. • Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN). • Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including SCAN, MBIST). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. • Optimizes logic to qualify the design to meet test-coverage, DPM, and test-time/vector-memory reduction goals as well as design integrity for physical implementation. • Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. • Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high-quality integration of the IP block. • Collaborates with post-silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation. Experiment in DFT for mix signal IP required. Qualifications: • Minimum Bachelor's degree in Electronics Engineering. • At least 4 years of experience in DFT. • Strong experience in Scan Architecture, Scan Insertion, and ATPG execution. • Experience defining and implementing scan procedures. • Good experience with Mixed-Signal IP DFT. • Hands-on experience with MBIST implementation and MBIST validation. • Experience in RTL design, DFT integration, verification, and supporting DFT activities at IP/SoC level. Job Type: Regular Shift: Shift 1 (Israel) Primary Location: Jerusalem, Israel Additional Locations: TLV Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Meet The Team The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. Your Impact • Develop and implement DFT features to ensure high-quality, testable, and manufacturable designs. • Contribute to the full product cycle, from pre-silicon design to post-silicon debug and production qualification. • Collaboration across multiple hardware teams throughout the silicon lifecycle. • Implement ATPG, scan compression, and memory BIST techniques to improve test coverage and efficiency. • Lead debugging and root-cause analysis of silicon failures to improve yield and reliability. • Establish DFT methodologies and best practices to improve the efficiency of future designs. Minimum Qualifications • B.Sc. in Electrical Engineering or a related field. • 3+ years of hands-on experience with one or more DFT domains, such as scan insertion, BIST, or boundary scan, silicon debug. • Experience with Automatic Test Pattern Generation (ATPG) methodologies. Preferred Qualifications • Strong ability to establish and refine DFT methodologies from design phase to high-volume production. • Ability to quickly learn new concepts and adapt to evolving technologies. • Excellent communication and presentation skills. • Strong attention to detail and system-level understanding of networking and silicon solutions. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Who We Are The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. The Design for Test (DFT) team is part of the design group, which focuses on logic design, RTL development, and running verification tests. Their main role is to design test structures embedded within the chip to ensure proper functionality after manufacturing. The goal is to detect potential manufacturing defects with maximum efficiency and filter out faulty units before they reach the market. What You'll Do • Insert DFT logic, perform synthesis, and run Automatic Test Pattern Generation (ATPG) to ensure hardware testability. • Execute Gate Level Simulations, timing checks, and DRC checks to maintain rigorous design integrity and performance standards. • Run regressions and perform deep-dive debugging on simulation failures as part of the core verification process. • Work in a small, agile team with an intimate atmosphere that offers direct mentoring and broad professional growth. Minimum Qualifications • B.Sc or M.Sc Electrical/Computer Engineering graduate from leading Israeli Universities with average grades above 85. • Team players who enjoy big challenges. • People who can quickly ramp on multiple, interdisciplinary domains. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Designs and develops integrated circuits. Oversees definition, design, verification, and documentation for ASIC development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development. - Knowledge: Having wide-ranging experience, uses professional concepts and company objectives to resolve complex issues in creative and effective ways. • Strong project management skills • Leads design and delivery of new products/process • Functional breadth and depth, plus expert in complementary fields • Applies broad concepts and theories to achieve innovative and effective solutions to complex problems - Job Complexity / Contribution : Works on complex issues where analysis of situations or data requires an in-depth evaluation of variable factors. Exercises judgment in selecting methods, techniques and evaluation criteria for obtaining results. Networks with key contacts outside own area of expertise. • Will champion significant projects, programs and business initiatives using demonstrated creativity and ingenuity • Team leader • Leads major projects • Influences or impacts others' priorities, decisions or activities • Escalation point for complex issues • Coaches and mentors other junior team members - Supervision : Incumbents provide a leadership role for the work group through knowledge in his/her area of specialization. Generally free to determine work priorities based on general direction from managers. • Determines methods and procedures on new assignments • Consults with management on long-range goals • Determines own priorities, both tactical and strategic - Experience : Bachelors and 8+ years of related experience; at this level post-graduate coursework may be desirable or Masters degree and 6+ years of related experience or PhD and 3+ years of related experience Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Mobileye's Automated Driving group is looking for an experienced DFT Engineer. This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting-edge technologies - Autonomous Vehicle (AV) SoC. At Mobileye's Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating! We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV). What will your job look like: • Develop all the necessary HW / FW / SW for the different modules. • Verify and Validate our design. • Debug and analyze coverage and yield loss. • As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts – as it required by the Automotive and Safety related products market (ISO26262). All you need is: • At least 5 years of experience in the ASIC/SoC industry. • Excellent communication skills. • BSc or MSc in Computer Engineering or Electrical Engineering. Nice to have: • Proven Experience in either SCAN or MBIST tools and flows. • Knowledge of Hierarchical SCAN methodology. • Knowledge of Logic BIST (LBIST) and Test Point Insertion (TPI) flows. • Knowledge of TAP protocols IEEE 1149.1/1500/1687 (iJTAG). • Knowledge of Synthesis flows. Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

What will your job look like: • Develop all the necessary HW / FW / SW for the different modules. • Verify and Validate our design. • Debug and analyze coverage and yield loss. • As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts – as it required by the Automotive and Safety related products market (ISO26262). All you need is: • At least 5 years of experience in the ASIC/SoC industry. • Excellent communication skills. • BSc or MSc in Computer Engineering or Electrical Engineering. Nice to have: • Proven Experience in either SCAN or MBIST tools and flows. • Knowledge of Hierarchical SCAN methodology. • Knowledge of Logic BIST (LBIST) and Test Point Insertion (TPI) flows. • Knowledge of TAP protocols IEEE 1149.1/1500/1687 (iJTAG). • Knowledge of Synthesis flows. Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

NVIDIA is looking for an experienced DFT Design Engineer to join the DFT design team and develop the next generation DFT technologies. As a design engineer in the DFT design team at NVIDIA, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals. What you'll be doing: • In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies. • As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production. • Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks. What we need to see: • B.Sc. in Electrical Engineering or Computer engineering or equivalent experience. • 5+ years of practical experience. • Exposure to rtl implementation and coding. • Familiarity with verification tools. • Strong debugging, problem solving and analytical skills. • Strong communication and social skills are required. • Ability to work in a geographically diverse team environment. • Self motivated, independent and target oriented. Ways to stand out from the crowd: • Prior Design or Verification experience. • Experience in developing sophisticated design blocks. • Integration of design elements to large cluster or full-chip. • Experience in working with back-end on area, power and timing closures. • Scripting ability. NVIDIA has some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of developing the next generation technologies? If so, we want to hear from you. Come, join our DFT Team for a challenging and educational environment, where every individual has a significant contribution to our products and achievements!

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Design-for-Test Engineering team at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing. Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements! What you’ll be doing: • You will be in charge of state of the art Design for Test/ATPG flows and implementation • Take full ATPG ownership end to end on a project, from Arch & planning to pattern generation, verification and post Silicon bring up and diagnosis. • Inventing and maintaining automation flows that provide the short test time to production What we need to see: • 5+ years of hands on DFT/ATPG experience knowledge & technical experience in DFT ASIC Design and in ATPG tools • Experience in Mentor TestKompress ATPG tool and retargeting flow • Strong programming skills in scripting languages • BSc. in Electrical Engineering or Computer engineering • Quick learner, proactive and self-motivated, eager to learn and contribute, sense or ownership, commitment, and responsibility Ways to stand out from the crowd: • Knowledge of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation • Programming languages: TCL, PRL, Phyton & Unix shell scripts • Experience with ATE and Silicon bring-up NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you're creative and autonomous, we want to hear from you! You will have the opportunity to work on some of the most incredible products on the market today.

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Engineering team at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing. Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements! What you’ll be doing: • You will be in charge of state of the art Design for Test/ATPG flows and implementation • Take full ATPG ownership end to end on a project, from Arch & planning to pattern generation, verification and post Silicon bring up and diagnosis. • Inventing and maintaining automation flows that provide the short test time to production What we need to see: • 5+ years of hands on DFT/ATPG experience knowledge & technical experience in DFT ASIC Design and in ATPG tools • Strong programming skills in scripting languages • BSc. in Electrical Engineering or Computer engineering • Quick learner, proactive and self-motivated, eager to learn and contribute, sense or ownership, commitment, and responsibility Ways to stand out from the crowd: • Knowledge of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation • Experience in Mentor TestKompress ATPG tool and retargeting flow • Programming languages: TCL, PRL, Phyton & Unix shell scripts • Experience with ATE and Silicon bring-up NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you're creative and autonomous, we want to hear from you! You will have the opportunity to work on some of the most incredible products on the market today.

NVIDIA is looking for an experienced DFT Engineer to join an exceptional team of DFT experts to develop the next generation DFT technologies. As a DFT engineer at the networking group at NVIDIA, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals. What you'll be doing: • In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies. • As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production. • Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks. What we need to see: • B.Sc. in Electrical Engineering or Computer engineering or equivalent experience. • 10+ years of practical experience. • Exposure to rtl implementation and coding. • Familiarity with verification tools. • Familiarity with backend flows. • Strong debugging, problem solving and analytical skills. • Strong communication and social skills are required. • Ability to work in a geographically diverse team environment. • Self motivated, independent and target oriented. Ways to stand out from the crowd: • Prior Design, Verification experience. • Experience in working with back-end on area, power and timing closures. • Experience with CDC flows and tools. • Experience with silicon testing. • Cad tool development experience. NVIDIA has some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of developing the next generation technologies? If so, we want to hear from you. Come, join our DFT Team for a challenging and educational environment, where every individual has a significant contribution to our products and achievements!

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Design-for-Test Engineering team at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing. Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements! What you’ll be doing: • You will be in charge of state of the art Design for Test/ATPG flows and implementation • Take full ATPG ownership end to end on a project, from Arch & planning to pattern generation, verification and post Silicon bring up and diagnosis. • Inventing and maintaining automation flows that provide the short test time to production What we need to see: • 3+ years of hands on DFT/ATPG experience knowledge & technical experience in DFT ASIC Design and in ATPG tools • Strong programming skills in scripting languages • BSc. in Electrical Engineering or Computer engineering • Quick learner, proactive and self-motivated, eager to learn and contribute, sense or ownership, commitment, and responsibility Ways to stand out from the crowd: • Knowledge of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation • Experience in Mentor TestKompress ATPG tool and retargeting flow • Programming languages: TCL, PRL, Phyton & Unix shell scripts • Experience with ATE and Silicon bring-up NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you're creative and autonomous, we want to hear from you! You will have the opportunity to work on some of the most incredible products on the market today.

Job Details: Job Description: Join us to help build the next generation of AI hardware solutions. You will be part of a highly skilled, agile team developing cutting-edge hardware for the AI domain, where we push the boundaries of what silicon can do for emerging AI workloads. We are building this team from scratch within Intel. With a startup-like culture, we move quickly and give engineers the opportunity to drive significant technical and business impact. We are intentional, fast adopters of AI as a working tool, and actively use AI throughout our architecture, design, verification, and development workflows. If you are energized by defining things that have never existed before, value rigorous thinking, and want real scope and short feedback loops, you'll feel right at home here. This is a senior, hands-on role with broad technical influence. You will own central DFT aspects in our new family of chips and will define their architecture, planning and implementation. You'll also play a central role at defining and improving the methodologies and workflows we adopt as a team. Responsibilities • Define DFT architecture and strategy for complex AI acceleration IPs and subsystems, balancing test coverage, area, timing, and power. • Build the DFT implementation - scan, compression, boundary scan (JTAG), MBIST, and test access/control - and drive fault coverage closure to sign-off. • Lead ATPG & pattern generation • Contribute to the development of DFT methodologies and working flows, helping drive best practices across the team. • Champion and advance the team's use of AI tools across the DFT flow, finding where they add real leverage and helping the team adopt them well • Collaborate closely with design, verification, physical design, and product/test engineering teams, and support silicon bring-up, debug, and yield/quality analysis. Qualifications: • B.Sc. in Electrical Engineering, Computer Engineering, or equivalent. • 6+ years of hands-on DFT experience, with a strong record of driving DFT solutions from architecture through silicon bring-up. • Deep command of core DFT techniques: scan insertion, compression, ATPG, boundary scan (JTAG), and MBIST. • Strong intuition for working with AI tools and real interest in using them to advance the DFT flow. • Demonstrated ownership of complex DFT solutions and the ability to drive technical decisions across cross-functional teams. Advantage • DFT experience on large, high-performance, or AI/ML accelerator designs. • Hierarchical DFT, low-power test, in-system test, or silicon debug/bring-up experience. • Strong familiarity with the broader development cycle, including design, verification, and physical design Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Haifa Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *