Retym

Description For an exciting well-funded start-up, we are looking for a Backend Team member. You will work on complex design, high frequency and low-power budget. Work on ramp-up full RTL2GDSII flow for leading technology and work with external vendors. Requirements Key responsibilities: • RTL-to-GDSII Ownership: execute the complete backend implementation flow (Logic Synthesis, P&R, Tape-Out, IR-drop, etc.), ensuring timely, first-pass silicon success. · Constraints & Timing Closure: Work with design and DFT engineers to write timing and physical constraints, and sign-off on the design using comprehensive Static Timing Analysis (STA), timing eco implementation. · Advanced Physical Implementation: Drive complex physical design tasks including Floorplanning, Power/Ground (PG) Mesh implementation, and handling advanced clocking (CTS/Clock-Mesh) and Hierarchical Design flows. · Low Power Expertise: Define, implement, and verify advanced low power design techniques to meet aggressive power consumption targets. · Design for Manufacturability: Implement and verify Design-for-Test (DFT) strategies and close physical verification challenges, specifically focusing on IR-Drop analysis. · IP Integration & Automation: Execute complex IP integration, incorporating blocks generated by memory compilers and other automated tools. • Collaboration: work closely with design team to understand the data path and correctly implement the floorplan, provide feedback on RTL changes required, Implement logical eco post RTL freeze with design team. • CAD: Improve existing implementation flows to achieve better QOR, write scripts for supporting the P&R flows. Minimum Qualifications • Experience of 5+ years in backend design • Strong expertise of full RTL2GDSII including: • Logic synthesis & equivalence checking • Constraints definition and writing • Complicated IP integration • Memory compilers and other automated block generators • DFT • Floorplanning, PG Mesh • P&R • Low power design including definition, implementation and verification • Timing STA • IR-Drop • BS/MS in EE/CE from lead universities Preferred Qualifications • Team player • Highly motivated • Learning abilities • Good communication • Work with external vendors • Experience in Synopsys/Cadence tools is an advantage • Low power techniques • Clock-mesh/ multi source cts • Hierarchical design flow • Experience in tape-out procedures • RTL code reading A very interesting job and good conditions are guaranteed to the candidates

Description We are seeking a skilled Production Test Engineer to join our team, specializing in high-speed mixed-signal ICs. In this role, you will be responsible for the execution, optimization, and continuous improvement of test processes for high-performance mixed-signal ICs in a high-volume manufacturing environment. You will ensure the devices meet stringent quality standards while working with cross-functional teams to optimize test methodologies, troubleshoot test failures, and improve yield. The ideal candidate will have experience with Automated Test Equipment (ATE), high-speed digital interfaces (e.g., SerDes), Analog circuit testing (e.g., ADCs, DACs, PLL), and mixed-signal ICs. Requirements Key Responsibilities • Test Execution & Monitoring • Execute test plans for high-speed mixed-signal ICs, ensuring all performance criteria are met before production release. • Perform automated testing on ATE platforms (e.g., Teradyne), focusing on both Analog and digital signal integrity, functionality, and power measurements. • Monitor the production line for test performance, ensuring that all ICs meet quality standards before being shipped to customers. • Troubleshooting & Debugging • Troubleshoot and identify root causes of test failures in high-speed mixed-signal ICs, collaborating with design and quality teams to resolve issues. • Perform failure analysis on devices that fail initial tests and implement corrective actions to prevent recurrence in future production runs. • Work closely with design engineers to refine and debug test programs for both digital and Analog components. • Test Optimization & Process Improvement • Continuously improve test flow, reduce test time, and optimize throughput without compromising quality or test coverage. • Participate in yield enhancement activities, analysing test data to identify patterns and implementing solutions to improve yield and reduce defects. • Automate repetitive test tasks and implement new testing procedures to ensure efficiency and accuracy. • Collaboration & Reporting • Collaborate with design engineers to ensure that the test process is optimized for the manufacturability of mixed-signal ICs. • Provide detailed test reports, including yield data, test results, and analysis of device performance. Share insights and recommendations with senior management to enhance production efficiency. • Test Equipment Management • Maintain and calibrate test equipment to ensure accuracy and reliability, including Automated Test Equipment (ATE), oscilloscopes, logic analyzers, and signal generators. • Ensure that test hardware is properly set up, configured, and validated for each new device under test (DUT). • Troubleshoot and resolve any issues related to test equipment functionality. Qualifications • Education: Bachelor’s degree in electrical engineering, or a related field. • Experience: 2+ years of experience in production testing of high-speed mixed-signal ICs or similar semiconductor devices. • Skills: • Hands-on experience with Automated Test Equipment (ATE) such as Teradyne, Advantest, or National Instruments. • Experience testing high-speed digital interfaces (e.g., SerDes) and Analog mixed-signal components (e.g., ADCs, DACs, amplifiers, PLL). • Familiarity with testing methodologies for signal integrity, timing analysis, and power consumption in high-speed devices. • Proficiency in using oscilloscopes, logic analyzers, and signal generators. • Experience with test data analysis and reporting tools. • Strong problem-solving and analytical skills to diagnose and resolve test failures. • Good communication skills to collaborate across engineering and production teams. • Ability to work efficiently in a fast-paced production environment with a focus on continuous improvement.

Description Overview The System Director Manager for Optical Digital DSP base Systems is a senior leadership role responsible for managing and directing the development, implementation, and optimization within optical communication networks. This position demands a comprehensive understanding of optical communications, DSP algorithms, system architecture, PCB design, and hands-on lab work. The System Director Manager will lead a team of engineers, ensuring the successful deployment of state-of-the-art optical DSP chip, while collaborating closely with other departments. Requirements Key Responsibilities • Leadership and Management: • Lead, mentor, and manage a team of engineers, providing technical guidance and fostering professional growth. • Develop and execute strategic plans for optical system development, aligning with organizational objectives. • Collaborate with cross-functional teams including , VLSI, Analog, and algorithm teams. and management to ensure seamless project execution. • Technical Oversight: • Oversee the design and development of advanced optical systems. • Ensure the effective integration of DSP Chip solutions into optical communication systems • Conduct technical reviews, offering feedback on system design, architecture, and implementation. • PCB Design and Lab Work: • Supervise the design, testing, and validation of PCBs used in optical DSP systems. • Manage lab activities, ensuring proper setup, maintenance, and operation of lab equipment. • Oversee hands-on lab work, including the assembly and testing of prototypes and final products. • Ensure compliance with safety and quality standards within lab environments. • Innovation and Research: • Drive innovation in optical DSP technologies by staying updated on industry trends and emerging technologies. • Promote a culture of continuous improvement and innovation within the team. • Project Management: • Manage project timelines, budgets, and resources to ensure timely delivery of DSP chip system solutions. • Develop and maintain comprehensive project documentation, including specifications, design documents, and test plans. • Coordinate with external partners and vendors as required. • Quality Assurance: • Implement best practices for system validation and testing. • Ensure the reliability and performance of systems through rigorous testing and analysis. • Oversee troubleshooting and resolution of issues in deployed systems. • Customer and Stakeholder Engagement: • Engage with customers to understand their requirements and provide technical expertise. • Present technical concepts and project updates to stakeholders, including executives and customers. • Ensure customer satisfaction with delivered DSP system solutions. Qualifications • Education: • B.Sc./M.Sc in Electrical Engineering, Computer Science, or a related field with a focus on signal processing or optical communications. • Experience: • 10+ years of experience in optical communications and digital signal processing. • Proven track record in leading and managing engineering teams. • Extensive experience in designing and implementing optical DSP chip systems. • Familiar with RTL Design, FW implementation and Analog-Mixed-Signal integrations. • Experience in PCB design and lab work. • Work with standards like OIF and IEEE, ITU, and other specifications • Skills: • Deep understanding of optical communication systems, including coherent optical systems, and fiber optics. • Proficiency in signal processing algorithms, including modulation, demodulation, equalization, and FEC. • Strong programming skills in languages such as MATLAB, Python, C/C++, and experience with DSP hardware. • Experience with PCB design software and PI/SI tools • Hands-on experience in lab work, including the use of oscilloscopes, spectrum analyzers, AWG, and other lab equipment. • Excellent project management and organizational skills. • Strong analytical and problem-solving abilities. • Effective communication and interpersonal skills. • Ability to work in a fast-paced, dynamic environment.

Description For an exciting well-funded start-up, we are looking for an excellent analog mixed signal engineer. You will develop high end ADC/DAC in advanced process for optical communication. Requirements Minimum Qualifications Expert: • Beyond 10 years experience with relevant Analog circuits • Leading analog design of complex analog systems such as PLL’s, DAC, ADC’s, SerDes from Concept and Architecture, specification and design • Leading Top-level of such complex blocks, technically leading other team members • Design, Development, and Verification of Integrated circuits - Analog and Mixed Signal Circuits – especially in advanced processes FinFet or GAA. • Advance degree from leading University in relevant field is an advantage. • Preferred Qualifications • Good Team Work • Good communication skills • Experience with Industry Standard custom/analog design tools • Understanding of layout and its requirements for high speed and low noise • Experience with Tape-Out and signoff requirements

Description For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Senior Verification Engineer to be driving into the complicated RTL design verification activity on various design aspects. Requirements Key responsibilities: • Ownership of block\cluster verification end to end from scratch. • Lead efforts of test bench architecture, Vplan definition and functional coverage. • Work closely with the design, architecture, algo teams and other stakeholders. • Support other team members and mentor less experienced engineers. Requirements • 10+ years of experience – a must • Performed at last 2 or more full block/system verification cycles. • In depth knowledge in VLSI verification flow, languages and concepts. • Experience in data path or data protocols, specifically Ethernet - preferred • Verification using one of the known methodologies (eRM, UVM, OVM). Responsibilities • Plan and perform the verification of digital design blocks according to the design specification and interacting with design engineers. • Build verification environments using SystemVerilog and UVM. • Identify and write all types of coverage measures for corner-cases. • Debug the functionality with design engineers. • Perform coverage collection and follow the metrices to close the full functionality.

Description For an exciting well-funded start-up, we are looking for an excellent analog mixed signal engineers. You will develop high end ADC/DAC in advanced process for optical communication. Requirements Minimum Qualifications Experience of 5+ years in advanced analog circuits This experience must include: • Above 5 years experience with relevant Analog circuits: • Such as PLL’s, DAC, ADC’s, SerDes, high-speed timing circuits, Phase-Interpolators etc.., including Top-level / system understanding of such complex blocks • Design, Development, and Verification of Integrated circuits - Analog and Mixed Signal Circuits – especially in advanced processes FinFet or GAA. • B.Sc/M.Sc in EE/CE from lead universities Preferred Qualifications • Good Team Work • Good communication skills • Experience with Industry Standard custom/analog design tools • Understanding of layout and its requirements for high speed and low noise • Experience with Tape-Out and signoff requirements

Description For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Mixed signal verification engineer. Requirements Key Responsibilities: • Develop verification strategies for digital and analog (mixed-signal) designs, utilizing UVM methodologies based on specifications. • Create behavioural models for analog blocks in accordance with guidelines provided by analog designers. • Write, execute, and debug testbenches using UVM methodology and SystemVerilog code for mixed-signal blocks. • Run and debug behavioural model (BM) validation using AMS tools to ensure the correctness of the behavioural models. • Perform and troubleshoot unit-level, cluster-level and top-level simulations of mixed-signal designs. Minimum Qualifications • 5+ years of experience • Experience in Behavioural Modelling (BM) of Analog design for digital verification • Knowledge in Mixed Signals dynamic Verification using chip digital design tools [no AMS] • Experience in Verilog/SystemVerilog coding • Experience in Virtuoso Schematics tools • Basic knowledge in Analog design Preferred Qualifications • Experience in UVM • Experience in both Synopsys and Cadence tools is an advantage Additional Skills • Verification Methodologies and Tools: Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases. • Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative team environment. • Communication: Strong communication skills, including the ability to write test plans, present results, and communicate clearly with multi-functional teams.

Description For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Mixed signal verification engineer. Requirements Key Responsibilities: • Develop verification strategies for digital and analog (mixed-signal) designs, utilizing UVM methodologies based on specifications. • Create behavioural models for analog blocks in accordance with guidelines provided by analog designers. • Write, execute, and debug testbenches using UVM methodology and SystemVerilog code for mixed-signal blocks. • Run and debug behavioural model (BM) validation using AMS tools to ensure the correctness of the behavioural models. • Perform and troubleshoot unit-level, cluster-level and top-level simulations of mixed-signal designs. Minimum Qualifications • 10+ years of experience • Experience in Behavioural Modelling (BM) of Analog design for digital verification • Knowledge in Mixed Signals dynamic Verification using chip digital design tools [no AMS] • Experience in Verilog/SystemVerilog coding • Experience in Virtuoso Schematics tools • Basic knowledge in Analog design Preferred Qualifications • Experience in UVM • Experience in both Synopsys and Cadence tools is an advantage Additional Skills • Verification Methodologies and Tools: Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases. • Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative team environment. • Communication: Strong communication skills, including the ability to write test plans, present results, and communicate clearly with multi-functional teams.

Description We are looking for a talented and experienced DFT Tech Lead. As a DFT Tech Lead you will work closely with all other design teams – backend, vlsi, verification and analog, fully responsible for defining, implementing, and deploying advanced design-for-test (DFT) methodologies for highly complex digital and mixed-signal chips. You will define silicon test strategies, DFT/DFD architecture, and create DFT and Debug specifications for complex next generation SoCs. Requirements Minimum qualifications: • 8+ Experience in DFT specification definition, architecture, insertion, and analysis in designs • Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG-related issues • Experience in fault modeling Preferred qualifications: • Master's degree in Electrical Engineering. • Experience in IP integration (memories, Test controllers, TAP, MBIST). • Experience using EDA Test tools like Design/Fusion Compiler, DFT Max, SpyGlass, Modus, Tessent, and TestKompress. • Experience and understanding of ASIC DFT, synthesis, simulation and verification flow. • Excellent attention to detail organizational, problem-solving, and communication skills. Responsibilities: • Create SoC DFT strategy and architecture (ATPG/DFT/MBIST) • Work on hierarchical design • Debug all Design Rule checks, apply design fixes to achieve high test quality • Insert all DFT logic - boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks. • Insert and hook up MBIST logic. • Define test plan for special analog IPs and implement. • Document DFT architecture and test sequences, including boot-up sequence associated with test pins.

Description For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Mixed signal verification Tean-Lead. Requirements • Lead and manage a distributed team of mixed-signal verification engineers across different time zones, ensuring smooth communication and collaboration. • Collaborate with analog and digital design teams to establish specifications, verification plans, and key milestones. • Define and oversee the development of behavioral models (BM) of analog designs, integrating them into digital verification flows. • Drive the execution of mixed-signal dynamic verification using industry-standard digital verification tools (excluding AMS). • Debug and resolve complex issues in mixed-signal designs, ensuring functionality and specification compliance. • Plan and implement scalable and reusable verification environments using Verilog/SystemVerilog. • Provide mentorship and technical guidance to team members, supporting their professional growth. • Manage project timelines, resource allocation, and reporting to ensure successful delivery of verification goals. Minimum Qualifications • 8+ years of experience in mixed-signal and/or digital mixed signal verification. • 3+ years of experience managing or leading verification teams. • Proven experience in Behavioral Modeling (BM) of analog designs for digital verification. • Expertise in mixed-signal dynamic verification using digital verification tools (excluding AMS). • Knowledge Verilog/SystemVerilog for building and debugging testbenches. • Experience with Virtuoso for analog schematic understanding and review. • Solid understanding of analog design fundamentals and concepts. Preferred Qualifications • Hands-on experience with UVM methodology. • Proficiency in both Synopsys or Cadence verification tools. Additional Skills • Verification Methodologies and Tools: Proven ability to develop scalable, portable test cases and utilize verification tools effectively, including simulators, waveform viewers, and coverage collection. • Collaborative Environment: Experience verifying analog/mixed-signal designs in a cross-functional, team-oriented setting. • Communication: Exceptional skills in writing test plans, presenting results, and communicating effectively with multi-disciplinary teams and stakeholders.

Description We are looking for an experienced, hands-on System Integration Engineer focused primarily on full optical-module integration and testing with various customer platforms. The role also covers bring-up and debugging from the silicon and board level to DSP and complete system solutions. It combines laboratory work, root-cause investigation, intermediate Python/MATLAB automation, and cross-functional collaboration. Requirements Responsibilities • Execute PCB bring-up procedures and validate boards for ASIC revisions. • Validate EVBs, reference designs, and optical modules. • Perform full optical-module testing and integration with customer platforms. • Develop and execute validation plans, test procedures, and regression tests. • Debug complex hardware, firmware, and system-level issues. • Validate power, clock, reset, and high-speed interfaces, including SerDes and optical links. • Develop Python/MATLAB automation for validation, characterization, and regression testing. • Operate and automate laboratory measurement equipment. • Analyze BER, eye quality, signal integrity, power consumption, and thermal behavior. • Work with hardware, firmware, and software teams to resolve system issues. • Characterize analog blocks, DACs, ADCs, PLLs, power supplies, and monitoring circuitry. • Review schematics and identify board-level issues. • Prepare validation reports and document debugging findings. • Support customer evaluations and reproduce customer-reported issues. • Prepare and deliver product demonstrations for customers. • Collaborate with customers, external partners, and vendors during integration activities. Required Qualifications • B.Sc. in Electrical Engineering or equivalent. • 6+ years of experience in hardware, system validation, or system integration. • Strong laboratory skills and experience with electronic measurement equipment. • Experience debugging complex electronic systems. • Intermediate Python proficiency for automation and data analysis. • Good understanding of digital interfaces and embedded systems. • Experience in digital signal processing (DSP) and communication systems. • Familiarity with power sequencing, voltage regulators, clocks, and reset architectures. • Ability to read schematics and perform board-level debugging. • Strong analytical and problem-solving skills. • Excellent communication and documentation skills. • Fluent English. • Availability to work fully on-site, five days per week. Preferred Qualifications • Experience with high-speed interfaces such as PCIe, Ethernet, and SerDes. • Experience with coherent optical DSPs. • Familiarity with CMIS, OIF, or OpenROADM specifications. • Understanding of Signal Integrity and Power Integrity. • Experience validating mixed-signal ASICs. • Experience with analog calibration techniques. • Experience with MATLAB/Python. • Experience working in multidisciplinary engineering teams. Personal Attributes • Hands-on and proactive. • Curious and driven to investigate root causes. • Strong ownership and accountability. • Excellent teamwork and communication skills. • Able to manage multiple activities in a fast-paced environment. • Detail-oriented, with a systematic approach to debugging.

Description For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Verification Team-Leader to be driving into the complicated RTL design verification activity on various design aspects. Requirements Key Responsibilities • Lead, mentor, and manage a team of verification engineers to meet project milestones and deliverables. • Define and execute verification strategies and plans for complex digital blocks and systems. • Oversee the development of robust and reusable verification environments using SystemVerilog and UVM. • Review and approve verification plans, testbenches, and coverage metrics. • Drive functional and coverage-based verification across multiple block/system verification cycles. • Collaborate with design engineers to debug and resolve functionality issues. • Ensure effective resource allocation and project planning to achieve optimal results. • Foster a culture of technical excellence, continuous learning, and innovation within the team. • Report verification progress, issues, and risks to senior management and other stakeholders. Required Qualifications • 8+ years of experience in digital design verification—a must. • 3+ years of experience managing or leading verification teams. • Proven track record of completing two or more full block/system verification cycles. • In-depth knowledge of VLSI verification flows, concepts, and methodologies. • Expertise in verification using SystemVerilog, UVM, or other industry-standard methodologies (eRM, OVM). • Experience with data protocols or data path designs (Ethernet experience preferred). • Experience with Ai, agent build, integration to flow and shorten verification cycle time. • Strong problem-solving skills and the ability to debug complex functionality issues. • Excellent leadership, communication, and organizational skills to manage and inspire a team. Preferred Qualifications • Hands-on experience with high-speed communication protocols like Ethernet, PCIe, or SerDes. • Proficiency in scripting languages (e.g., Python, Perl) for automation of verification processes. • Familiarity with formal verification techniques and tools. • Background in system-level verification or post-silicon validation. • Experience with project planning tools and methodologies for effective team management.

Description For an exciting well-funded start-up, we are looking for a Backend Team member. You will work on complex design, high frequency and low-power budget. Work on ramp-up full RTL2GDSII flow for leading technology and work with external vendors. Requirements Key responsibilities: • RTL-to-GDSII Ownership: execute the complete backend implementation flow (Logic Synthesis, P&R, Tape-Out, IR-drop, etc.), ensuring timely, first-pass silicon success. · Constraints & Timing Closure: Work with design and DFT engineers to write timing and physical constraints, and sign-off on the design using comprehensive Static Timing Analysis (STA), timing eco implementation. · Advanced Physical Implementation: Drive complex physical design tasks including Floorplanning, Power/Ground (PG) Mesh implementation, and handling advanced clocking (CTS/Clock-Mesh) and Hierarchical Design flows. · Low Power Expertise: Define, implement, and verify advanced low power design techniques to meet aggressive power consumption targets. · Design for Manufacturability: Implement and verify Design-for-Test (DFT) strategies and close physical verification challenges, specifically focusing on IR-Drop analysis. · IP Integration & Automation: Execute complex IP integration, incorporating blocks generated by memory compilers and other automated tools. • Collaboration: work closely with design team to understand the data path and correctly implement the floorplan, provide feedback on RTL changes required, Implement logical eco post RTL freeze with design team. • CAD: Improve existing implementation flows to achieve better QOR, write scripts for supporting the P&R flows. Minimum Qualifications • Experience of 10+ years in backend design • Strong expertise of full RTL2GDSII including: • Logic synthesis & equivalence checking • Constraints definition and writing • Complicated IP integration • Memory compilers and other automated block generators • DFT • Floorplanning, PG Mesh • P&R • Low power design including definition, implementation and verification • Timing STA • IR-Drop • BS/MS in EE/CE from lead universities Preferred Qualifications • Team player • Highly motivated • Learning abilities • Good communication • Work with external vendors • Experience in Synopsys/Cadence tools is an advantage • Low power techniques • Clock-mesh/ multi source cts • Hierarchical design flow • Experience in tape-out procedures • RTL code reading A very interesting job and good conditions are guaranteed to the candidates

Description As System Validation engineer, you will play a crucial role in designing, testing, and troubleshooting Analog circuits within a laboratory setting. Your expertise in Analog electronics and proficiency in operating laboratory equipment will contribute to the development of cutting-edge products. Requirements Qualifications: Educational Background: BSc in Electrical Engineering Professional Experience: • Minimum 5 years of experience in test development, debugging, and reporting for mixed-signal Integrated Circuits (ICs). Technical Expertise: • Lab Equipment Proficiency: Extensive hands-on experience with a variety of lab equipment, including but not limited to: • Digital Multimeters • Source Meters • Spectrum Analyzers • Signal Generators • High speed Oscilloscopes • Power Supplies • Logic Analyzers • Bit Error Rate Testers (BERT) • Arbitrary Waveform Generators (AWG) • PCB Review: Reviewing expertise in PCB schematic design using OrCAD and layout design using Allegro for analog and mixed-signal applications, including FPGA-based designs. • Automation and Analysis: Skilled in test automation and utilizing data analysis platforms. • Coding Skills: Good coding and scripting abilities in languages such as C/Python/Matlab • Analog Circuit Design: Experience in analog circuit design. • Component Testing: Proven track record in testing critical components such as Phase-Locked Loops (PLL), Delay-Locked Loops (DLL), Serializer/Deserializer (SERDES), Low-Dropout Regulators (LDO), Analog-to-Digital Converters (ADC), Digital-to-Analog Converters (DAC), and voltage references. • Communication and Leadership: Strong communication and interpersonal skills. Demonstrated leadership abilities for driving cross-functional test plans and debug activities. Advantageous Skills: • Signal Integrity (SI) / Power Integrity (PI): Familiarity with SI/PI debug and check. • Optical Interconnect System: Familiarity with optical interconnect systems, including components such as optical transceivers, fiber optics, and photodetectors. • Fast SerDes Interfaces: Experience with high-speed Serializer/Deserializer (SerDes) interfaces, including design, testing, and performance optimization. • Coding Skills: Perl, Tcl, etc.

Description For an exciting well-funded start-up, we are looking for a DSP Optical Communication Algorithm senior engineer. As an Algorithm Engineer you will be part of the R&D group developing next generation coherent optical transceivers for DCI with data rates of 800Gbps and 1600Gbps. You will design, simulate, and optimize algorithms. You will interact with many different teams such as: Analog, System, VLSI, Design Verification and FW. What will your work look like? • Design and simulate DSP architectures, define key capabilities, performance requirements and drive specifications for analog, digital and firmware designers. • Develop and simulate DSP algorithms and behavioral models of the optical channel, the optical-electrical transceivers and analog units (ADC/DAC). • Work with designers to ensure circuit architecture can be efficiently implemented. • Participate in cross-functional teams with analog, digital, and firmware designers for bring-up and validation/optimization activities. Requirements Required Experience • 5 years or more of hands-on experience and a well proven record of modem algorithms development (Clock Recovery, Equalization, Phase Recovery, and tracking) for Single Carrier modulation and demodulation. • Fixed point design and programming in MATLAB and C • Very good understanding of System and HW implementation restrictions (from MATLAB to RTL) • Lab hands on (algorithms debug and tuning) Additional Preferred Experience • Experience with Optical Communication systems • Understanding analog mixed signal (ADC/DAC/PLL/VCO) and specifications • Experience with analog circuit calibrations Educational Background: BSc in Electrical Engineering

Description We are looking for talented and experienced VLIS Design Engineers/Micro-architects. As an VLIS Design Engineer/Micro-architect, you'll have the opportunity to design highly sophisticated, innovative new cutting edge communication systems from scratch. In this position you will be responsible for coming up with creative solutions to architectural challenges and crafting the very fine details of the implementation Requirements Job requirements: • 5 years of experience as ASIC/FPGA designer • Strong Verilog/System-Verilog experience • Familiar with simulation tools/environments, verification methodologies • Strong team player, solid interpersonal skills • Entrepreneurial can-do attitude, self-motivated, able to work independently • BS/MS in EE/CE from lead universities Background in one or more of the following domains is an advantage: • Familiar with advanced design practices (Clock/Voltage domain crossing, Low Power Design, DFT) • Design DSP of oriented blocks • Ethernet (100G and above) • Scripting experience using several of the following: Python, Perl, TCL