Majestic Labs

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position  In this high-impact role, you are the bridge between cutting-edge custom silicon and production-grade AI. You will own the end-to-end LLM serving stack on Majestic hardware, architecting everything from serving APIs down to KV cache management, batching, and scheduling. Your primary mission is to port leading frameworks like vLLM and SGLang to our accelerator and optimize them for peak performance. Because our architecture offers memory headroom, you won't just match traditional GPUs; you will shatter their limits on throughput, batch sizes, and context lengths. As you hunt down bottlenecks, your insights will directly steer our future kernel, compiler, and hardware development. Responsibilities  • The serving stack, end to end — bring up and adapt a modern inference framework (vLLM, SGLang, or similar) to run on Majestic hardware. • The runtime hot path — continuous batching, the scheduler, paged KV cache, and prefill/decode disaggregation. • Distributed inference at scale — tensor, pipeline, and expert parallelism across accelerators, wired into our collective communication library (CCL). • The multi-modal pipeline — image, audio, and video preprocessing, encoder integration, and mixed-modality batching. • Inference-time techniques — speculative decoding, prefix caching, and structured decoding. • End-to-end performance — profile, benchmark, and hunt down bottlenecks across the full serving path, feeding findings back to the kernel, compiler, and hardware teams. Requirements • 5+ years building or operating production LLM inference and serving systems. • Deep, hands-on work with a modern inference framework vLLM, SGLang, TensorRT-LLM, Fireworks, or similar including its scheduler, paged attention / KV cache, model executor, and backend integration points. • Strong Python and C++, with the ability to move fluidly between the two. • A real grasp of transformer inference the prefill/decode split, KV cache behavior, and how batching dynamics shape latency and throughput. • Distributed inference experience tensor and pipeline parallelism across multiple devices. • An instinct for performance you can profile an end-to-end stack and chase a regression from the serving API all the way down to the kernel. We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position  • Design and implement high-performance compute kernels for AI primitives such as GEMM, attention, normalization, and convolution. • Optimize for throughput, latency, and memory hierarchy across heterogeneous compute units (SIMD, matrix engines, DMA). • Collaborate with compiler and runtime teams to integrate kernels into Triton and PyTorch pipelines. • Profile and tune kernels using tools like Perfetto, VTune, Tracy, Nsight, or custom simulators. • Prototype and evaluate precision formats (FP16/BF16/FP8/e5m2, MXFP/FP4, etc.). • Contribute to micro-architecture feedback loops, helping co-design ISA and memory features with the hardware team. Requirements • Degree at any level in Computer Science, Computer Engineering, or a related field from a recognized university. • Strong background in parallel programming (CUDA, Triton, RISC-V Vector (RVV), POSIX Threads, or OpenMP). • Deep understanding of memory layout, vectorization, thread/block scheduling, and cache behavior. • Experience programming wide-SIMD vector units and matrix/systolic engines. • Familiarity with the parallel-computing ecosystem and its high-performance libraries and • primitives, such as BLAS/BLIS, dense linear algebra, and parallel scan/reduce/sort. • Skilled in performance analysis and parallel debugging using tools such as GNU Debugger and Nsight. • Hands-on experience profiling and optimizing compute or AI workloads (e.g., GEMM, softmax, attention). • Solid grasp of numerical stability, precision formats, and mixed precision arithmetic. • Proficiency in C++17 or higher, with strong knowledge of standard algorithms, data structures, and generic programming paradigms. • Collaborative work style with the ability to operate effectively in multicultural, cross-disciplinary environments. Preferred qualifications  • Experience with optimization of irregular algorithms, such as graph computations or sparse • numerical linear algebra, combining high-level data structure design with low-level SIMD and synchronization optimizations. • Familiarity with LLVM/MLIR. • RISC-V systems or bare-metal programming, including RISC-V vector and matrix extensions. We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position  We are building the next generation of AI infrastructure-from custom silicon to the servers and systems that power the world's largest AI models. Our vertically integrated approach enables us to optimize every layer of the AI compute stack, delivering breakthrough performance, efficiency, and scalability. We're looking for an experienced Product Manager who thrives at the intersection of the data center server grade hardware, systems engineering, and AI. In this role, you will define product strategy and execution for AI accelerator platforms, server architectures, and infrastructure products that enable true best-in-class inference on frontier-scale models. You will work closely with silicon architects, hardware/systems engineers, software teams, AI researchers, operations, and executive leadership to bring complex products from concept through deployment. Responsibilities  • Product Management / Operations: own the server product definition: chassis, thermals, power, serviceability, cabling, rack integration, ODM requirements, data center compatibility, and the translation of architecture into a buildable server specification. • Define product feature set. Translate customer, engineering, and business requirements into detailed Product Requirements Documents (PRDs), technical specifications, and feature definitions. • Own and develop detailed product schedules, milestone plans, and release timelines while managing dependencies across all engineering teams. • Product Strategy: • Develop near, mid- and long-term product strategy and roadmap for next generation product spanning custom silicon, server platforms, and system-level architecture. • Develop near, mid- and long-term product strategy for modified product configurations and new product lines. • Articulate product vision, success metrics and product positioning in the market . • Prioritize features, functionality, and technical investments based on customer value, competitive landscape, engineering complexity, and business objectives. • Product reviews, executive updates, and roadmap planning with senior leadership. • Interfaces: • Architecture team to jointly analyze emerging AI workloads and translate them into future hardware and system capabilities. • System engineers and ODM to optimize deployment, performance, power efficiency, cooling, networking, and total cost of ownership. • Software teams to ensure seamless integration across firmware, drivers, runtime software, orchestration, and AI frameworks. • Bizops to develop competitive analyses across AI infrastructure providers, hyperscalers, semiconductor companies, and emerging AI platform vendors. Requirements • 10+ years of product management experience across data center infrastructure, server hardware, cloud platforms, semiconductors, AI systems, or distributed systems. • Proven track record of leading highly technical, multidisciplinary infrastructure products from concept through scaled production. • Expertise in developing PRDs, technical specifications, and product roadmaps while driving prioritization, milestones, and release planning. • Strong analytical and communication skills, with the ability to make data-driven decisions and align executive stakeholders with deeply technical engineering teams. Preferred qualifications  • M.S. or Ph.D. in Computer Science, Electrical Engineering, Computer Engineering, Artificial Intelligence, Machine Learning, Applied Physics, or a related technical discipline. • MBA or equivalent in product strategy or technology commercialization. • Product management experience at large hyperscaler/neo-clouds, frontier AI labs and AI HW/server companies, or similar organizations developing large-scale AI systems. We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position  We are building the next generation of AI infrastructure-from custom silicon to the servers and systems that power the world's largest AI models. Our vertically integrated approach enables us to optimize every layer of the AI compute stack, delivering breakthrough performance, efficiency, and scalability. We’re looking for a visionary, highly technical Senior Product Manager who thrives at the intersection of data center infrastructure, server-grade hardware and software, systems engineering, and AI to lead our AI software stack, compiler platform, and server system software. This role is responsible for defining and delivering the software ecosystem that makes Majestic's system completely seamless for developers and cloud infrastructure teams. You will own the compiler roadmap, runtime engines, and framework integrations that translate standard deep learning model representations into highly optimized execution paths on the Ignite APU. Responsibilities  • Translate customer, engineering, and business requirements into detailed Product Requirements Documents (PRDs), technical specifications, and feature definitions. • Develop detailed product schedules, milestone plans, and release timelines while managing dependencies across multiple engineering organizations. • Compiler Pipeline and Toolchain Roadmap: Define requirements for the software and AI model compilation toolchain • Framework Integration and Interoperability: Lead product partnerships and technical integrations with major machine learning frameworks and runtimes, ensuring native support for PyTorch, JAX, vLLM, SGLang, and Hugging Face Optimum without requiring customer code modifications. • High-Performance Kernel Optimization Roadmap: Define performance optimization roadmap for low-level operator libraries, including BLAS, custom OpenAI Triton kernels • Scale-Out and Clustering Orchestration: Define requirements for clustering and multi-node scale-out configurations, ensuring seamless execution across scale-out setups utilizing SLURM, Ray, LMCache, etc. • Developer Platform Usability: Act as the primary advocate for developer experience, monitoring how software compiles and executes in customer sandboxes, and proactively removing the need for manual memory management scripts, custom compiler hacks, or API wrappers. Requirements • Education: Master of Science (M.Sc.) or Doctor of Philosophy (Ph.D.) in Computer Science, Electrical Engineering, Mathematics, or Physics is a strict, non-negotiable requirement. • AI Software Stack Expertise: Minimum of 5 to 8 years of experience in product management or software systems engineering, with a proven track record of shipping compiler technologies, deep learning frameworks, or developer platform tools. • Parallel Programming Fluency: Deep theoretical and practical understanding of CUDA, Triton, high-performance C++ DSP libraries, and multi-threaded parallel computation paradigms. • Scale-Out Infrastructure Knowledge: Demonstrated familiarity with HPC scale-out infrastructures, distributed memory architectures, and networking protocols designed for high-performance clustering. • Prior experience at accelerated software, cloud, or startup organizations building complex AI compute systems, such as NVIDIA, Meta, Google, AWS, SambaNova, Cerebras, Groq, or Lightning AI. Preferred Qualifications  • MBA or equivalent experience in technology commercialization or product strategy. • Active contributions to open-source AI infrastructure projects, compilers (MLIR/LLVM), or performance optimization libraries. • Direct experience working inside a frontier AI lab or foundation model organization (e.g., OpenAI, Anthropic, xAI, Google DeepMind) developing large-scale distributed systems. We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position  We are looking for a Senior Signal Integrity (SI) and Power Integrity (PI) Engineer to own end-to-end electrical link performance across our high-speed interconnects - from architecture and pre-silicon modeling through silicon bring-up, validation, and high-volume manufacturing (HVM). This is a hands-on technical role for someone who has taken multiple products from concept to production and knows what breaks (and why) once real volume hits the line. Responsibilities  • Own signal integrity and power integrity analysis for end-to-end high-speed links, including package, connector, PCB, and cable interconnects • Drive SI/PI closure for high-speed SerDes interfaces (112G/224G-class), PCIe (Gen5/Gen6+), and parallel/single-ended interfaces such as DDR/LPDDR memory and chip-to-chip links • Perform pre-silicon channel modeling, budgeting, and margin analysis using COM (Channel Operating Margin), IBIS-AMI, and statistical eye methodologies • Build and correlate 3D/2.5D EM models (HFSS, PowerSI) against lab measurement (VNA, TDR, BERT, scope) to validate channel and package performance • Perform system-level power delivery network (PDN) analysis, decoupling strategy, and power/SI co-design across chip, package, and board • Use ADS and MATLAB for circuit-level simulation, link budget analysis, and custom post-processing/automation of simulation and lab data • Support silicon bring-up, debug, and characterization in the lab; root-cause SI/PI-related failures and drive corrective actions • Partner with ASIC, package, PCB layout, and mechanical teams to define design rules, stackups, routing guidelines, and connector/material selection • Lead products through DVT/PVT and into high-volume manufacturing, including establishing test limits, correlating ATE/system-level test data to simulation, and resolving field/yield issues tied to SI/PI margin • Contribute to internal methodology, tooling, and design guideline development. Requirements • 10+ years of hands-on SI/PI engineering experience in the semiconductor, systems, or networking hardware industry • Demonstrated experience across the full product lifecycle — architecture through production and sustained high-volume manufacturing — not just simulation-only roles • Deep working knowledge of high-speed SerDes signaling, including 224G (or comparable leading-edge) electrical interfaces, and PCIe link architecture • Solid experience with parallel/source-synchronous interfaces such as DDR/memory buses and chip-to-chip interconnects • Proficiency with COM-based analysis and IBIS-AMI modeling for channel compliance and margin assessment • Strong command of industry-standard tools: Ansys HFSS, Ansys PowerSI (or equivalent 2.5D/3D field solvers), Keysight ADS, and MATLAB • Hands-on proficiency with SI/PI lab testing and validation equipment, including Vector Network Analyzers (VNA) for S-parameter extraction, TDR/TDT for impedance and discontinuity characterization, and oscilloscopes for eye diagram, jitter, and signal quality measurement • Familiarity with power integrity fundamentals — PDN impedance analysis, decap strategy, DC/AC drop, and chip-package-board co-design • Experience working with cross-functional teams (ASIC design, package engineering, PCB layout, test/ATE, manufacturing) to drive designs to closure • Excellent written and verbal communication skills; able to clearly present technical risk and trade-offs to both engineering and program stakeholders Preferred Qualifications  • Experience with additional high-speed standards (CXL, Ethernet SerDes) • Scripting/automation experience (Python) for simulation flow automation or data analysis • Experience with connector, cable, or optical module electrical characterization • Familiarity with signal/power co-simulation and chip-package-system (CPS) modeling flows • Exposure to compliance testing and industry standards bodies (PCI-SIG, OIF-CEI, JEDEC) We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position  • Architect & Implement: Research, design, and deliver hardware-and-software security architectures for our next-generation AI Inference Systems, ensuring alignment with global security standards. • Root of Trust & Boot: Own the micro architectural definition, validation, and rollout of the SoC Hardware Root of Trust (RoT) and secure boot processes. • Confidential Computing & Isolation: Apply advanced hardware primitives to implement secure software compartmentalization, isolating critical AI assets and model IPs from multi-tenant threats. • Secure Software Embedding: Collaborate directly with software and research teams to embed secure firmware, model-protection mechanisms, and open-source security frameworks into the silicon platform. • Threat Modeling: Build and execute data-driven threat models to identify, validate, and mitigate hardware and low-level firmware vulnerabilities. • Cross-Functional Ownership: Lead security feature implementation from conceptual modeling and emulation through to customer deployment and threat resolution. Requirements • Education: BSc, MS, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or equivalent experience. • Experience: 10+ years of proven track record in hardware security architecture, silicon design, or embedded security engineering. • Secure System Building: Deep, practical understanding of "Security-by-Design" principles, privilege isolation, and Confidential Computing concepts. • Firmware & Low-Level Dev: Strong programming and debugging fundamentals in C/C++, Python, and assembly (e.g., ARM) with hands-on experience in low-level firmware and embedded systems. • Execution & Teamwork: A proven track record of leading complex technical features across diverse, cross-functional teams, backed by excellent communication skills. Preferred Qualifications  • Direct experience with Linux security primitives, secure hypervisors, or microkernel architectures. • Background in high-performance networking security (RDMA, TCP/IP, TLS/IPSec) • Experience mitigating AI-specific hardware threats (e.g., side-channel analysis, fault injection). We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position  We are looking for an experienced, highly skilled and motivated Senior Compiler Engineer to join our compiler team. In this role, you will be responsible for designing, developing, and maintaining critical components of our AI-driven compilation stack. You will work on PyTorch, Triton, LLVM, and MLIR to build robust, scalable, and high-performance solutions for diverse hardware backends. This is a hands-on technical position where you will solve complex problems, optimize for performance, and contribute to the next generation of our technology. Responsibilities  • Design, Implement, and Optimize Compiler Components: Architect and develop critical compiler modules to efficiently translate and optimize AI models for deployment across a variety of hardware platforms, including CPUs, GPUs, and emerging custom accelerators • Enhance and unify PyTorch Inductor, Triton, LLVM, and MLIR toolchains to support cutting-edge architectures, facilitate seamless interoperability, and enable rapid experimentation with new compiler features • Create and maintain custom IRs, code generation passes, and optimization strategies tailored for AI workloads, focusing on both general and domain-specific improvements • Profile and tune computational kernels—such as linear algebra operations, matrix multiplications, and elementwise computations—to achieve optimal performance, scalability, and resource efficiency on diverse hardware • Open-Source Engagement: Actively contribute to the LLVM, MLIR, Triton, and PyTorch open-source projects, sharing improvements, collaborating with the developer community, and driving the evolution of the AI compiler ecosystem. Requirements • Bachelor’s or Master’s in Computer Science, Computer Engineering, or a related field from a recognized university • 7+ years experience in compiler engineering or closely related fields • Deep knowledge of LLVM and MLIR internals, including IR transformations, code generation, and backend optimization techniques • Experience with PyTorch (Inductor/Dynamo) and Triton, including their compiler subsystems • Proven experience and expertise in C/C++ programming • Demonstrated expertise in performance optimization, including vectorization, parallelization, and hardware-specific tuning • Advanced debugging, analytical, and system-level thinking skills • Excellent communication skills with a strong track record of cross-functional collaboration Preferred Qualifications  • Strong understanding of AI models - both training and inference pipelines • Experience developing compiler support for custom hardware accelerators, including ASICs, FPGAs, or novel AI chips • Active contributions to open-source compiler frameworks, demonstrating leadership and community involvement • Familiarity with distributed training strategies, graph compilers, and advanced memory models We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position  This is a highly technical and cross-functional role requiring deep expertise in SoC networking, high-speed interconnects, and protocol acceleration for AI. As a SOC System Network Architect for AI, you will lead the definition and architectural design of network engines and interconnect fabrics powering our custom AI servers. You will collaborate closely with silicon architecture, hardware design, firmware, and software teams to shape scale-up and scale-out networking topologies optimized for distributed AI workloads. Responsibilities  • Architect end-to-end SoC networking engines, SmartNIC/NIC architectures, and switch interface IPs for AI accelerators • Define scale-up (intra-node) and scale-out (inter-node) network topologies • Design hardware acceleration and offload engines for AI collective operations (e.g., AllReduce, AllGather, AllToAll) directly on the network fabric • Optimize transport protocols (RoCEv2, custom RDMA engines, TCP/UDP offloads) and adaptive routing/congestion control algorithms (e.g., DCQCN) for synchronized AI traffic flows • Drive performance modeling, cycle-accurate simulations, and traffic pattern analysis to evaluate architectural trade-offs across network fabrics • Collaborate with ASIC design, silicon architecture, and AI software teams to define hardware/software interfaces, register abstractions, and programming models • Produce high-quality network architecture specifications, interface documents, and lead cross-functional architecture reviews Requirements • 7+ years of hands-on network architecture, SoC interconnect design, or silicon engineering experience, with at least 3 years in an architecture or technical lead capacity • B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or Computer Science • Proven track record of owning and delivering complex network ASICs, NIC engines, or switch architectures from initial concept through silicon bring-up Core Technical Skills  • Deep expertise in SmartNIC/NIC architecture, RDMA technologies (RoCEv2, InfiniBand), and hardware transport protocol engines • Strong understanding of scale-up and scale-out topologies, high-speed packet processing, and switch architecture trade-offs • In-depth knowledge of AI communication patterns and hardware acceleration for network collective operations • Solid foundation in lower-level network protocols (TCP/UDP, Ethernet, IP) and advanced network congestion control mechanisms • Proficiency in network performance modeling, hardware simulation tools, and architectural trade-off analysis Preferred Qualifications  • Experience with high-speed proprietary interconnects (e.g., NVLink, NVSwitch, UALink, CXL) or custom switch silicon • Hands-on experience with network simulation and modeling frameworks (e.g., ns-3, OMNeT++, SystemC/TLM) • Familiarity with distributed AI communication libraries (e.g., NCCL, RCCL) and frameworks (PyTorch, DeepSpeed) We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position  We are looking for an experienced, highly skilled and motivated Software Engineer to join our core team. In this role, you will be responsible for designing, developing, and maintaining critical components of our AI-driven software stack. You will work on the core interfaces that allow applications, frameworks, and APIs to communicate efficiently and reliably with our hardware. This is a hands-on technical position where you will solve complex problems, optimize for performance, and contribute to the next generation of our technology. Responsibilities  • Develop and maintain key components of Majestic software stack, including API layers, command submission pipelines, and memory management • Collaborate with hardware architects to influence the design of next-generation chips and ensure a smooth software/hardware co-design • Work with kernel-space driver developers to define and implement the user/kernel interface • Debug complex issues across the entire stack, from user applications to the underlying hardware • Optimize code for maximum performance, throughput, and efficiency Requirements • Bachelor’s or Master’s in Computer Science, Computer Engineering, or a related field from a recognized university • Proven experience developing software for Linux, with a solid grasp of OS fundamentals like memory management, multi-threading, and inter-process communication • 5-10 years of experience in software development • Proven experience in C programming • Knowledge in GPU programming • Excellent communication skills with a strong track record of cross-functional collaboration Preferred Qualifications  • Experience with Python and C++ • Knowledge of GPU or other accelerator architectures (e.g., CUDA, OpenCL, ROCm) • Knowledge of HPC applications development • Experience in linux kernel-space development We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position  We are looking for an experienced, highly skilled and motivated Pre-Silicon Verification Engineer to join our core team. In this role, you will be responsible for chip-level and performance verification of one of our custom ASICs. Responsibilities  • Work with our engineers and partners to help verify our ASICs • Work with our architecture team to understand our architecture and to design end-to-end test flows and methodologies to verify real-world performance scenarios • Manage vendors and/or contractors as necessary Requirements • Bachelor’s or Master’s in Computer Science, Computer Engineering, or a related field from a recognized university • Expert-level experience with simulation tools & flows (VCS, Verdi, NCSim and the like) • Scripting experience in Perl and/or Python • 5+ years experience using constrained random & functional coverage based verification methodologies on large design blocks • 5+ years hands-on coding of UVM verification environments • C/C++ expertise is a plus • Excellent communication skills and a strong track record of cross-functional collaboration Preferred Qualifications  • Experience with and understanding of common LLMs • Experience with AI or other large-scale datacenter-grade ASICs • Experience doing performance verification of compute or networking ASICs We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position  We're seeking an experienced Technical Program Manager with operational expertise to lead large-scale, cross-functional engineering programs, unblocking development bottlenecks, mitigating risks, and translating complex system architecture into actionable timelines for internal teams and ODM partners. This is a hybrid role that bridges technical depth with operational rigor - you'll manage complex, multi-disciplinary projects involving hardware design, procurement, deployment, network architecture, and preparation to scale. This role encompasses coordinating multiple suppliers and manufacturing partners, optimizing production workflows, and ensuring we deliver servers reliably to meet customer commitments. You'll work closely with silicon, software and systems engineers, ML teams, as well as business and operations to ensure our products are robust, reliable, and production-ready. Responsibilities  • Own end-to-end program management for projects spanning compiler infrastructure (IR design, optimization passes, codegen), custom AI kernel development, and GPU runtime/scheduling systems • Partner closely with compiler engineers, kernel developers, and systems architects to build realistic roadmaps, break down complex technical work into sequenced milestones, and track progress against them • Identify and manage cross-team dependencies • Translate ambiguous technical goals into scoped, actionable project plans • Run planning ceremonies and surface technical risk early • Coordinate with hardware and silicon partners on integration timelines, driver dependencies, and co-design feedback loops • Maintain project documentation, architecture decision records, and technical roadmaps in collaboration with engineering leads Requirements • 10+ years in program/project management, including 5+ years leading technically complex, multi-stakeholder programs • Track record of managing multi-team technical programs with interdependent workstreams and hard performance/correctness requirements • Strong operational background: defining processes, metrics, and driving efficiency • Technical fluency in data center, networking, or compute infrastructure; able to engage deeply with engineers • Conceptual familiarity with AI compute, distributed training, or inference systems • Excellent written/verbal communication across technical and non-technical audiences • Proficiency with Jira, Asana, Monday.com, or similar; comfort with data/metrics dashboards Preferred Qualifications  • Software development experience with infrastructure projects like storage, OS, and hardware bring-up. • Experience managing or scaling data center operations, cloud infrastructure (AWS, GCP, Azure), or hyperscaler / on-premises server deployments • Background in DevOps, infrastructure engineering, or site reliability engineering (SRE) • Experience with AI/ML infrastructure, GPU clusters, or distributed computing systems • PMP, CAPM, or equivalent program management certification • Previous role in a high-growth tech or AI company • Analytical, data-driven decision-making with a metric-driven mindset (dashboards, KPIs) • Comfortable with ambiguity; able to bring clarity and proactively manage risk and contingency • Strong stakeholder influence, collaborative leadership, and attention to both detail and big-picture outcomes We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position  We are looking for a Researcher/Architect to work on AI workload characterization and simulation and translating architectural ideas into quantitative, defensible performance models. This role is ideal for someone who lives at the intersection of: • Computer architecture • Workload characterization • System-level modeling • AI / data-intensive workloads Responsibilities  Performance simulator & translate workloads into models  • Extend and maintain system-level performance models (compute, memory, interconnect, scheduling). • Model system behaviors: NUMA effects, contention, coherence, bandwidth saturation. • Characterize real workloads (LLMs, GNNs, graph analytics, tabular models and more). Guide architectural decisions  • Evaluate architectural trade-offs • Produce quantitative comparisons vs. existing and emerging AI platforms. • Work closely with hardware architects, compiler/runtime teams, and external partners. • Ensure simulator assumptions align with hardware and software reality. Support external conversations  • Contribute to technical deep dives with strategic partners and customers. • Help translate performance modeling into clear narratives for execs and investors. Requirements • BSc in CS, EE, CE or similar degrees plus 8 years experience in computer architecture, systems research, or performance engineering. Or PhD in CS, EE, CE or similar degrees plus 2 years of relevant experience. • Strong background in performance modeling or simulation (analytical, event-driven). • Experience with AI or graph workloads. • Understanding of: memory hierarchies (NUMA, caches, coherence), Interconnects (PCIe, fabrics, RDMA-), GPU-based systems. • Hands-on coding experience (Python, C/C++, or similar). • Ability to reason from first principles, not just benchmarks. Preferred Qualifications  • Background in computer architecture simulators • Exposure to AI/ML runtimes, compilers, or hardware-aware model design. • Research background (MS/PhD) in computer systems (CS/EE), architecture, or related fields. We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position  We are seeking a highly skilled Senior Power Engineer to take a leadership role in defining the board-level and rack-level power delivery architecture for our next-generation, multi-kilowatt AI server platforms. This critical position owns the end-to-end design of high-current power delivery paths to advanced SoCs, encompassing the definition of voltage conversion and regulator strategy, comprehensive Power Delivery Network design including efficient decoupling schemes, and driving critical design tradeoffs to maximize efficiency, optimize thermal performance, and ensure overall system performance, all while considering compatibility with OCP/Open Rack power distribution standards. You will work cross-functionally with silicon, mechanical, thermal, and systems engineers to deliver robust, efficient, and scalable power delivery for these complex platforms. Responsibilities  • Architect and design board-level, server-level, and rack-level power delivery systems for high-power subsystems. • Define PDN topology, including VRMs, POLs, vertical and lateral power routing, and high-current interfaces. • Perform component selection (VRMs, FETs, inductors, bulk caps, MLCCs, connectors, busbars) and create derating, margin, and reliability guidelines. • Lead decoupling capacitor strategy across package and PCB layers to meet target impedance and transient response goals. • Drive power integrity analysis (AC/DC, Z-target, transient, EMI/EMC) and validate designs through modeling, simulation, and lab measurement. • Collaborate with mechanical and thermal teams to ensure high-current routing, cooling requirements, and system constraints are aligned. • Partner with silicon and package engineering to co-design vertical PDN paths, including socket interfaces, pin/bump maps, and transient load profiles. Review and advise silicon design to improve power integrity. • Develop test plans for PDN validation, transient load tests, impedance measurement, and system bring-up. • Provide expertise during failure analysis, root-cause investigations, and corrective actions for system power issues. Requirements • BS/MS in Electrical Engineering or related field. • 10+ years of experience in high-power delivery design. • Demonstrated experience designing high-current, low-voltage power delivery for SoCs. • Deep expertise in power integrity, PDN modeling, VRM design, target impedance definition, and transient response optimization. • Proficiency with SPICE, PDN simulation tools (Keysight, Cadence Sigrity/Clarity, Ansys SIwave), and measurement equipment (VNAs, oscilloscopes, electronic loads). • Solid understanding of package-to-PCB PDN interactions. • Strong communication and cross-functional collaboration skills. Preferred Qualifications  • Familiarity with EMI/EMC mitigation in high-current environments. • Experience in server-class PCB design, including stackup planning, high-current routing, and decoupling strategies • Background in thermal-mechanical co-design for high-power modules. • Knowledge of rack-level power architectures, ORv3/OCP standards, power shelves, and busbar system We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position  We are looking for an experienced Silicon Technical Program Manager (TPM) to help manage our vendor's backend execution and New Product Introduction (NPI) for our data-center-grade AI chips. In this role, you will bridge hardware design, backend implementation, and post-silicon qualification, characterization and validation. You will drive multi-chip execution schedules from RTL freeze through physical implementation, tapeout, post-silicon characterization, qualification, and high-volume production release. Requirements • Bachelor of Science (BS) in Electrical Engineering, Computer Engineering, or related technical field with 8+ years of direct silicon engineering and silicon program management experience, OR • Master of Science (MS) with 6+ years of relevant experience. • Backend Expertise: Hands-on background or direct program management experience in physical implementation tasks. • Post-Silicon & NPI Experience: Proven track record bringing complex chips from tape out to mass production. • Data-Center Class Silicon: Demonstrated experience executing high-power data-center-grade silicon projects. • Cross-Functional Rigor: Excellent technical communication skills with a proven ability to challenge technical trade-offs across backend design, DFT, and product engineering teams. Preferred Qualifications  • AI Silicon Experience: Direct experience managing silicon for specialized AI accelerators or GPUs. We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position  This is a highly technical and cross-functional role requiring deep expertise in embedded systems, low-level protocols, and platform bring-up. You will collaborate with hardware design, silicon architecture, software, and security teams to shape both current products and future roadmaps. Responsibilities  • Architect and lead firmware development for complex platform • Own end-to-end firmware design • Define firmware architecture for out-of-band (OOB) server management, thermal management, power sequencing, and firmware update pipelines • Collaborate with silicon teams to influence hardware design decisions • Lead silicon bring-up activities • Define and enforce firmware security architecture • Produce high-quality architecture documents, firmware interface specifications, and design reviews Requirements • 7+ years of hands-on firmware or embedded systems engineering experience, with at least 3 years in an architecture or technical lead capacity • B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or Computer Science • Proven track record of owning and delivering complex firmware subsystems from architecture through mass production Core Technical Skills  • Deep expertise in System Control Processor firmware design - power management, boot sequencing, platform initialization, complex memory initialization • Hands-on experience with communication protocols design and implementation • Strong C programming skills for bare-metal and RTOS-based embedded environments • Deep understanding of server platform architecture: power delivery, thermal management, and hardware root of trust and secure boot Preferred Qualifications  • Background in NVLink, NVSwitch, or GPU interconnect firmware • Contributions to open-source firmware projects (OpenBMC, Zephyr RTOS) We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position  We are seeking an experienced SoC Architect - AI Acceleration (RISC-V and Compute Cluster Development) to lead the architecture and integration of Majestic’s compute subsystem. In this role, you will define and optimize the RISC-V-based compute clusters, vector engines, and shared memory structures that power high-performance AI workloads. You’ll collaborate closely with design, verification, compiler, and ML software teams to define architectures that maximize performance per watt while ensuring scalability across multiple generations of silicon. This is a hands-on technical leadership role for an architect who thrives at the intersection of hardware design, parallel compute, and AI acceleration. Responsibilities  • Architect and define RISC-V compute clusters, including multi-core integration, interconnects, and memory subsystems. • Design matrix multiplication and vector processing engines optimized for neural network and ML kernels. • Define the ISA extensions, microarchitecture, and system-level interfaces supporting AI acceleration. • Develop strategies for compute task mapping, thread scheduling, and shared cache (L3) utilization. • Collaborate with compiler and ML runtime teams to ensure software–hardware co-optimization. • Evaluate performance and power trade-offs across workloads using simulation and modeling. • Define debug, trace, and performance-monitoring features at the compute-subsystem level. • Work with SoC, memory, and I/O architects to ensure cohesive dataflow and system efficiency. • Provide specifications and technical guidance for RTL, verification, and firmware implementation teams. Requirements • Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or related field. • 10+ years of experience in SoC or compute architecture, with a focus on AI acceleration or high-performance compute. • Deep understanding of RISC-V architecture, vector extensions, and parallel compute design. • Experience with multi-core cluster integration, shared memory hierarchies, and cache coherency protocols. • Familiarity with matrix multiplication engines, SIMD/vector processors, and AI kernel optimization. • Strong background in embedded systems architecture, system-level performance modeling, and debug methodologies. • Excellent analytical, problem-solving, and communication skills Preferred Qualifications  • Experience designing custom RISC-V ISA extensions or AI-specific compute units. • Hands-on work in neural network mapping, tiling, and kernel scheduling. • Familiarity with AXI, UALINK, HBM, or chiplet-based architectures for scalable AI compute. • Contributions to open-source RISC-V or AI compute frameworks. • Proven success in first-silicon AI or HPC SoC programs. • Understanding of compiler design and low-level ML operator optimization. We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position  We are looking for a seasoned SoC Architect to lead the design and integration of the management subsystem within Majestic’s AI acceleration platform. In this role, you will define and drive SoC-level architecture for control and management flows — integrating ARM cores, interconnects, high-speed IO, and system management interfaces. You’ll collaborate closely with peer architects, hardware, firmware, and system engineers to ensure a cohesive, high-performance design that bridges silicon and software seamlessly. This is a hands-on architecture role that combines technical depth, system-level thinking, and cross-domain leadership in a fast-moving startup environment. Responsibilities  • Define and own the management subsystem architecture for Majestic’s AI SoC. • Integrate ARM cores (CSS / Cortex-A) and associated subsystems for control, configuration, and monitoring. • Architect PCIe connectivity and high-bandwidth IO to ensure robust host and device communication. • Specify and integrate DDR/LPDDR interfaces and memory management structures. • Design peripheral and control interfaces, including SPI, I2C, UART, GPIO, and system control buses. • Develop scheduler and interrupt schemes, driver-facing control paths, and configuration frameworks. • Integrate and optimize debug and trace infrastructures (CoreSight, profilers, diagnostic tools). • Collaborate with RTL, verification, firmware, and board teams to ensure seamless hardware-software co-design. • Drive tradeoffs and decisions to achieve performance, power, and area targets across the SoC. Requirements • Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or related field. • 6+ years of experience in SoC architecture and design, with emphasis on management or control subsystems. • Proven experience with ARM core integration, PCIe, DDR/LPDDR, and peripheral interfaces (SPI, I2C, UART). • Strong understanding of SoC design flows, memory hierarchy, and interconnect fabrics. • Hands-on experience in control path design, driver interfaces, and interrupt management. • Solid communication and teamwork skills, with the ability to lead cross-functional architectural discussions. Preferred Qualifications  • Experience with AI/ML acceleration hardware or high-performance compute SoCs. • Knowledge of board-level integration and hardware-software co-validation. • Familiarity with silicon prototyping, emulation, or FPGA-based validation. • Expertise in low-power design and high-bandwidth interconnect architectures. • Deep experience with debug tools (CoreSight, trace analyzers, profilers) and performance instrumentation. We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!