Intel

Job Details: Job Description: We are looking for a Hands-On Firmware Team Lead to lead a Firmware Power Management team within the Client PM Firmware Group and drive end-to-end PM feature development for Intel Client SoCs. The role combines deep technical ownership with team leadership, leveraging AI-driven flows and agents to accelerate architecture, development, debug, analysis and validation coverage closure. In this role, you will act as a player-coach, spending roughly 60 percent of your time on hands-on architecture and codebase development, and 40 percent guiding, mentoring, and managing a small team of specialized firmware engineers. You will collaborate closely with SoC architecture, hardware and validation teams to deliver highly efficient and stable power management firmware that delivers the most efficient power and performance flows. *Work Model: 4 days Onsite . Key Responsibilities: • Technical Leadership: Architect and develop robust embedded C++ firmware for power regulation, dynamic voltage scaling (DVFS), voltage/current management, and ultra-low-power sleep states. • Team Management: Lead, mentor, and conduct code reviews for a high-performing team of firmware engineers; manage project timelines, resource allocation, and team effectiveness. • Hardware Co-Design: Partner with Silicon Architecture and RTL design teams to define HW/FW interfaces and flows. • System Optimization: Drive power profiling, latency optimization, and firmware stability across bare-metal. • Testing Validation: enhance unit testing and system simulation frameworks to support developed set of features. Qualifications: • Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or a related discipline. • Firmware Expertise: Minimum 8 years of professional embedded firmware development experience using C and C++. • Leadership Experience: 2+ years leading engineering projects, mentoring junior developers, or directly managing engineering personal. • In-depth knowledge of embedded system mitigations, including RTOS. • Hands-on experience writing bare metal firmware code for ARM or Xtensa CPUs. • Domain Knowledge: Deep understanding of power management and state transitions, low-level firmware development and working with HW teams- Advantage Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Haifa Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *

Job Details: Job Description: Join us to help build the next generation of AI hardware solutions. You will be part of a team developing cutting-edge HW for the AI domain, where we push the boundaries of what silicon can do for emerging AI workloads. We are continuously developing modern and effective working methods, including hands-on adoption of AI tools throughout the chip development flow. The environment is fast-paced and intellectually stimulating. Your Mission: Integrate hardware security IP into the SoC/die and define the HW security architecture protecting a large-scale data center's compute, network, and control infrastructure. Responsibilities: • Integrate third-party and internal HW security IP (Root of Trust, crypto engines, HSMs, TRNG, key vaults) into the die; write and own the RTL/integration code wiring these units into the SoC. • Author RTL for security units, glue logic, fuse/OTP interfaces, and bus/fabric (AXI/AHB/NoC) connections; manage clock/reset/power domains and CDC. • Develop integration test benches, run lint/CDC/synthesis-readiness checks, and support DV/verification of the embedded security IP. • Architect platform Root of Trust, secure boot, attestation, and confidential computing (TDX/SGX/SEV-equivalent) across the server fleet. • Threat-model the full stack (silicon, firmware, BMC, supply chain) and define HW mitigations against physical and side-channel attacks. • Drive secure key management, debug-lockdown, fuse provisioning, and crypto offload for tenant isolation at scale. • Collaborate closely with architecture, design verification, physical design, firmware, and platform teams throughout the development cycle. Qualifications: • B.Sc., M.Sc., or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related field. • 5+ years of experience in RTL development, SoC design, or hardware security integration. • Proficient in Verilog/SystemVerilog RTL, IP integration, bus protocols (AXI/AHB/NoC); lint, CDC, synthesis, DV flows. • Expertise in roots of trust, TEEs, secure boot/firmware, crypto IP, side-channel mitigations. • Plus: fuse/OTP provisioning, supply-chain security, multi-tenant cloud isolation. Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Haifa Additional Locations: Israel, Petah-Tikva Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *

Job Details: Job Description: Intel Central Engineering Group (CEG) team delivers best-in-class Ethernet products and is at the heart of Intel's transformation from a PC company to a company that powers the cloud and billions of smart, connected computing devices. CEG's compelling Ethernet products move the world's data and are the foundations of cloud service and telecommunications data centers. You will be exposed to High-Speed I/O protocols such as PCIeGen6-7, DDR5-6, and PAM4 Ethernet 224Gb, which are a part of our Ethernet Infrastructure Processing Unit (Intel IPU) and Foundation NIC (FNIC) Ethernet product lines. We propose a dynamic and flexible workplace position, working directly with highly capable design, system, and pre/post-silicon teams within the organization. Most of the team's engineers have 10+ years of experience, and we are looking for a highly skilled multidisciplinary engineer with proven experience in Signal Integrity engineering to lead the hardware design of our next division projects' challenges and be part of Ethernet networking's accelerated growth. In this position, as a signal integrity engineer, you will be responsible for modeling channel elements in 3D and 2D EM simulation tools for pre- and post-layout stages of package and platform design for PCIe, Ethernet, and memory interfaces. You are expected to have a thorough understanding of RF circuits and electromagnetic wave propagation; the role includes learning the specifications of each interface and the required design limitations that should be verified. You will be expected to lead all signal integrity activities related to multiple projects for various high-speed and low-speed interfaces utilizing traditional and automated tools. You will work closely with silicon design teams and Hard IP vendors and will be responsible for the model's correlation based on cross-section and electrical measurements at the post-manufacturing stage and modeling manufacturing variation impact on the channels. You will be responsible for running the sign-off simulation flows for various designs, providing feedback to the design teams, and being hands-on in the lab for experiments when required. You would also be responsible for identifying/qualifying new AI-based automation techniques and solutions and providing technical leadership to working groups/task forces through debugging and reviews. Qualifications: Required Skills and Experience • B.Sc./M.Sc. Electrical Engineer with over 7 years of relevant experience in Signal Integrity • Proven design experience in the semiconductor ASIC development industry is a MUST • Proven planning and design flow buildup • Proven experience with PCB technology and layout techniques (Analog and Digital) including stack-up, routing, and advance SI/PI consideration • Proven hands-on experience with EDA tools: HFSS, CST, ADS, Simbeor, or equivalent • Knowledge of CAD tools: Cadence Allegro or Mentor Expedition, or equivalent • Proven experience with modeling and simulation one of the Ethernet, PCIe, DDR interfaces • Familiar with layout technics • Working experience with AI-based tools • Lab hands-on experience in high-speed, low-speed, and clocks circuitry signals measurement such as high-end Oscilloscopes, VNA, TDR, BERT's, etc. • Excellent debugging skills, ability to analyze problems, diagnose the root cause and apply corrective actions • Ability to work as a team player and contribute in a cross-functional product team on a daily basis • Strong verbal and written communication skills in English for interacting with design, evaluation and production engineers; customers; technical marketing engineers; and program managers Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Petah-Tikva Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *

Job Details: Job Description: Intel Central Engineering Group (CEG) team delivers best-in-class Ethernet products and is at the heart of Intel's transformation from a PC company to a company that powers the cloud and billions of smart, connected computing devices. CEG's compelling Ethernet products move the world's data and are the foundations of cloud service and telecommunications data centers. You will be exposed to High-Speed I/O protocols such as PCIeGen6-7, DDR5-6, and PAM4 Ethernet 224Gb, which are a part of our Ethernet Infrastructure Processing Unit (Intel IPU) and Foundation NIC (FNIC) Ethernet product lines. We propose a dynamic and flexible workplace position, working directly with highly capable design, system, and pre/post-silicon teams within the organization. Most of the team's engineers have 10+ years of experience, and we are looking for a highly skilled multidisciplinary engineer with proven experience in electrical and system engineering to lead the hardware design of our next division projects' challenges and be part of Ethernet networking's accelerated growth. The role requires high-frequency signal and power integrity and a good understanding of RF circuits and electromagnetic wave propagation. It includes learning the specifications of each interface and the required design limitations that should be verified. You will lead a team of developers and develop yourself digital and analog circuit boards for use in HW-Engineering products. In this position, your responsibilities include but are not limited to developing board design from schematic through leading the Silicon power-on hardware enablement and debug and may interface with other board design and test module development teams to drive innovation initiatives. You would also be responsible for identifying/qualifying new hardware solutions; providing technical leadership to working groups/task forces to resolve hardware, schematics, layout, and DFx issues through debugging and reviews; and part/component selection management. Qualifications: Required Skills and Experience - B.Sc./M.Sc. Electrical Engineer with over 10 years of relevant experience - Proven design experience in the semiconductor ASIC development industry is a MUST - Proven planning and design-flows buildup - Proven experience with PCB technology and layout technics (Analog and Digital) including stack-up, placement, routing, and advance SI/PI consideration - Knowledge of signal integrity, transmission line theory, analog circuits, and high-speed signal processing - FPGA and Verilog coding skills - Excellent debugging skills, ability to analyze problems, diagnose the root cause and apply corrective actions - Lab hands-on experience in high-speed, low-speed, and clocks circuitry signal measurements - Experience with debugging at circuit board-level problems in analog and digital domains using lab test equipment - Operating test equipment such as high-end Oscilloscopes, VNA, TDR, BERT's, etc. - Programming skills in one or more language such C++/python/MATLAB - Working experience with AI-based tools - Ability to work as a team player and contribute in a cross-functional product team on a daily basis - Strong verbal and written communication skills in English for interacting with design, evaluation and production engineers; customers; technical marketing engineers; and program managers - Comprehensive understanding of system architecture Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Petah-Tikva Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *

Job Details: Job Description: In this position, you will be working in the UPW (Ultra pure water) group in F28 facilities organization in Kiryat Gat, in order to verify systems are functioning well, performing all maintenance activities on the equipment and monitoring the equipment constantly. Systems activities include: Read and Rounds, coordination and management of activities, performance of repairs and advanced trouble shooting of equipment (which includes mechanical and electronic systems) and management of excursions based on RFC'S. Qualifications: You should be studying towards a Practical Engineer degree (הנדסאות ולא הנדסה) in Mechanical, Mechatronics, Water, or Chemical with at least 1.5 years till graduation and with the ability to work 2-3 days a week. Additional qualifications include: • High level and experience with EXCEL, ACCESS, and Microsoft Office • Multitasking and ability to work in parallel on many tasks • Ability to work in a team with good team relations • Ability to prioritize • High Technical skills and ability • Ability to work independently • High customer orientation • Good communication skills • High ability to express verbally and in writing in English Job Type: Student / Intern Shift: Shift 1 (Israel) Primary Location: Israel, Kiryat-Gat Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. *

Job Details: Job Description: As part of Intel's Core Engineering Group, we develop Intel's main and most valuable and complex IP: the Intel Performance Core. The Core is the central component of many Intel products, including desktops, notebooks, servers, cloud CPUs, and emerging AI platforms. Our Core technology powers hundreds of millions of products every year and drives innovations across cloud computing, AI, networking, communications, and consumer markets. The team is responsible for developing and managing critical mechanisms at the heart of Intel's next-generation Performance Core architecture. Our work has a direct impact on performance, power efficiency, scalability, and product competitiveness across Intel's CPU portfolio. About the Job We are looking for an experienced Logic RTL Design Engineer to join the Out-of-Order team. In this role: • you will define micro-architecture, develop RTL, and drive the implementation of complex allocation and resource management mechanisms in Intel's high-performance CPU cores. • You will own features from architecture exploration through RTL development, validation support, debug, and tape-in readiness. • You will lead significant design efforts, drive micro-architectural tradeoff discussions, and collaborate closely with architecture, verification, physical design, power-performance, and post-silicon teams. This is a unique opportunity to influence core technologies that directly impact CPU performance, power efficiency, and scalability while contributing to future generations of Intel Core products. Qualifications: • B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field. • At least 5 years of experience in RTL logic design and development using SystemVerilog. • Strong understanding of computer architecture, micro-architecture, and digital design principles. • Experience defining and implementing complex micro-architectural features. • Strong debugging and problem-solving skills. • Ability to independently drive features from definition through implementation and validation. • Excellent communication and teamwork skills. • Experience collaborating with architecture, validation, design, and post-silicon teams. • Nice to Have • Experience with design partitioning and micro-architectural tradeoff analysis. • Experience developing functional validation and coverage plans together with verification teams. • Experience working on high-performance CPU or cache/memory subsystem designs. • Experience with timing closure, power optimization, and performance analysis. • Knowledge of power-aware RTL coding methodologies and power debugging techniques. • Familiarity with advanced design methodologies, scripting, and automation. • Experience working with geographically distributed and cross-functional engineering teams Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Haifa Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *

Job Details: Job Description: We are seeking an experienced Senior CPU Debug Engineer to join our dynamic team. As a Senior CPU Debug Engineer, you will play a critical role in the development of our Core CPU, collaborating closely with our Architecture and Design teams, and providing top-notch customer debug support. Our goal is to ensure that Intel CPU Cores are of highest quality and performance, allowing our customers to build the best platforms in the market. Key Responsibilities: • Logic Debug: Lead and actively participate in the logical debugging of our Core CPU designs. Analyze and resolve complex logic issues that may arise during the validation process as well in customer field. • Collaboration: Partner with Architecture and Design teams to ensure CPU implementation aligns with architectural intent, while driving DFD and DFX methodologies. • Customer Support: Act as a technical point of contact for customers, addressing their queries, issues, and debugging requests. Provide timely and effective solutions to customer problems, maintaining strong relationships. • Debugging Tools: Develop and maintain debugging tools and methodologies to facilitate efficient CPU debugging. Stay up-to-date with the latest industry standards and tools to enhance debugging capabilities and innovate game changer DFD • Continuous Improvement: Continuously identify opportunities for improvement in the CPU debug process,techniques, and tools. Implement process enhancements to increase efficiency and reduce debugging time. • Collaborate with Hardware, Software, and Validation teams worldwide to ensure seamless CPU integration and system functionality. Qualifications: • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. • 5+ years of experience in CPU debugging, with a focus on Core CPU logic and design. • Strong knowledge of CPU architecture and design principles. • Excellent problem-solving skills and the ability to tackle complex issues efficiently. • Exceptional teamwork and communication skills to collaborate with cross-functional teams. • Knowledge of CPU verification techniques is a plus. Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Haifa Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *

Job Details: Job Description: In this position, you will be responsible for the plant electrical systems - including: distribution systems from site main substation at 161KV down to H.V, M.V systems at 22KV, 6.6KV and down below to various low voltages systems as LVSS's (Low Voltage Substations), UPSs, Emergency generators, Motor Control Centers, Variable Speed Drives and more. You will be responsible for the systems reliability and efficiency and you will be expected to drive continuous improvement to these systems. As part of the job you will also participate in different site technology projects design, you will be requested to lead electrical projects and to conduct startup and commissioning of new systems. Qualifications: What we are looking for? • BSc. in Electrical Engineering. • 5-12 years of experience as an Electrical Engineer in an industrial environment. • Israeli Electrical license - Electrical Engineer - (Hasmalai Mohandes). • Knowledge of industrial electrical system design principles, protection coordination, and selectivity. • Excellent verbal and written communication skills both in Hebrew and in English. • Knowledge and usage of Microsoft office and engineering design applications. • Deep technical engineering knowledge with good analytical and problem solving skills. • Good ability to work independently and a good team work. • High leadership and influence capabilities. • Customer orientation approach. Preferred Qualifications: • M.Sc. in Electrical Engineering. • Experience working in industrial plants or manufacturing facilities. • Israeli Electrical Inspector License (Bodek level 3). Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Kiryat-Gat Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *

Job Details: Job Description: Intel's Real Estate & Workplace Services (REWS) organization creates and maintains world-class work environments that enable employees to innovate and thrive. REWS is responsible for managing and operating Intel's global portfolio of offices, laboratories, and manufacturing facilities while advancing sustainability, operational excellence, and employee experience. We are seeking an experienced Construction Project Manager to join our team for a 36-month temporary assignment supporting Intel's Israel R&D campuses. Role Overview As a Construction Project Manager, you will lead the planning, coordination, and execution of diverse construction projects that support Intel's business objectives. Working closely with business units, facility operations, finance, procurement, architects, engineers, contractors, and suppliers, you will be responsible for delivering projects safely, on schedule, within budget, and to the highest quality standards. Key Responsibilities • Lead multiple construction projects from concept through completion across Intel Israel R&D sites. • Manage project scope, schedule, budget, quality, and risk to meet business requirements. • Coordinate with internal stakeholders and external partners, including architects, engineers, contractors, design-build firms, and quality assurance teams. • Ensure compliance with local regulations, permitting requirements, and Intel standards. • Promote a safe work environment by adhering to Intel Environmental, Health and Safety (EHS) requirements and supporting incident investigations when needed. • Translate business and technical requirements into practical, cost-effective, and constructible design solutions. • Drive innovation by implementing modern construction practices and engineering solutions. • Support sustainability initiatives, energy efficiency programs, and smart-building technologies. • Foster strong partnerships and contribute to a culture of operational excellence, customer focus, and continuous improvement. Qualifications: • Bachelor’s degree in Engineering, Construction Management, or a related field with 4+ years of relevant experience, or a Master's degree with 3+ years of experience. • Minimum of 3 years of construction leadership experience in roles such as Construction Project Manager, Engineering Manager, Design Manager, Site Construction Manager, or equivalent. • Demonstrated experience managing medium-scale construction projects and programs. • Ability to effectively engage with senior management while maintaining a hands-on approach when required. • Strong stakeholder management and cross-functional collaboration skills. • Excellent communication skills in both English and Hebrew, written and verbal. • Proven leadership, problem-solving, and decision-making capabilities. • PMP, PMBOK, CMP, or other project management certifications. • Experience with sustainable building practices, energy efficiency initiatives, and smart-building technologies. This role is ideal for a results-driven construction professional who thrives in a dynamic environment and is passionate about delivering innovative workplace solutions that enable Intel's continued success. This is a temporary position for 24 months. Job Type: Intel Contract Employee Shift: Shift 1 (Israel) Primary Location: Israel, Haifa Additional Locations: Israel, Jerusalem, Israel, Petah-Tikva Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. *

Job Details: Job Description: About us: Intel Networking team delivers best in-class Ethernet products and is at the heart of Intel's transformation from a PC company to a company that powers the cloud and billions of smart, connected computing-devices. We are a team of problem solvers, experimenters, and innovators who are dedicated to designing the network technologies that currently lead and continue to transform datacenter ecosystems. As a world-class organization, we're looking for outstanding talent to accelerate our growth during an exciting time in Ethernet networking marketing technology. If you're ready to be a part of this journey, then we want to hear from you. Job Description: Verification of the microarchitecture using industry standard Formal Verification tools and technologies based on latest model checking and equivalence checking algorithms on world class design IPs. Using the hardware architecture design and RTL implementation details, define the Formal Verification scope, deploy the right strategy to prove the correctness while deploying advanced formal techniques, and create abstraction models for convergence on the design, Carve out the right boundaries for the design, create comprehensive Formal Verification test plans, track, verify, apply abstraction techniques and converge on complex designs to deliver a high quality design on schedule and articulate the ROI. analyze new methodologies, evaluates new tools and corroborate results. May work with vendors on resolving hard design and tool problems. Qualifications: Minimum Qualifications: 3+ years of experience in Formal Verification Preferred Qualifications: Experience with Jasper, SVA, Jasper Apps (connectivity, coverage) Experience with Perl/Python Experience with GHCP and AI tools Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Haifa Additional Locations: Israel, Jerusalem, Israel, Petah-Tikva Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. *

Job Details: Job Description: Power management architect for Intel Architecture group, take part in the definition of the state-of-the-art CPU end to end power handling. Defines active and idle power management solutions, interaction with OS, driver and platform components. You will acquire understanding in CPU architecture and micro architecture, deep understanding in power scenarios, power delivery and power efficiency schemes. The primary focus of this position is to define next generation CPU power management architecture, deliver architectural specifications. You will initiate, guide and coordinate overall design of new ideas and products, drive for implementation and activation in post Si. Intel is in the world's top leaders of chip power and energy management. You will join part of experienced technical architecture leading team, inventing and driving innovative technologies solutions at Intel and Industry Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering or related field 6+ years of related work experience Experience in SW writing and definition (C/C++,python, C#) OR experience in aspects of Chip design and a development (electrical components, logical flows, CPU architecture). Deep understanding in system architecture and state of the art CPU design for PC or mobile devices Ability to deal with ambiguity, strong analytics and problem solving skills to achieve high quality results; Strong interpersonal skills (with proven track record of cross group collaboration) Self-motivated, customer oriented, resourceful and enthusiastic, showing an intense customer mind-set. Strong debugging experience and excellent problem solving skills. Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Haifa Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *

Job Details: Job Description: We are looking for a senior security researcher to lead advanced vulnerability research in confidential computing technologies. This role combines deep technical expertise with organizational leadership — spanning exploit development, architecture reviews, and executive-level influence on product security strategy. What You'll Do • Lead complex vulnerability research across firmware, software, virtualization, and hardware security domains • Conduct architecture security reviews, threat modeling, secure code reviews, and red team assessments • Develop innovative analysis techniques, fuzzing frameworks, and security research tools • Communicate complex technical findings to executives, engineering leaders, and external stakeholders • Mentor and develop security researchers at various experience levels What We're Looking For • Passion for security research and a demonstrated attacker's mindset • Strong technical leadership with the ability to influence without direct authority • Proven experience leading ambiguous, high-impact technical investigations • Ability to balance hands-on technical work with strategic leadership responsibilities Qualifications: • 4+ years of experience in security research, offensive security, or a related field. • Proven track record of identifying significant security vulnerabilities and driving remediation • Demonstrated experience leading complex security research or offensive security projects • Degree, or equivalent experience, in Computer Science, Computer Engineering, or a related field • Extensive hands-on experience in C/C++ software development and security analysis • Deep understanding of modern security principles, attack techniques, and defensive technologies • Experience influencing technical decisions across multiple teams or organizations • Strong analytical, technical leadership, and communication skills • Fluency in English Preferred Qualifications: • Experience in penetration testing, fuzzing, reverse engineering, exploit development, and static code analysis • Expertise in embedded software and firmware security • Deep understanding of OS internals, virtualization technologies, and compiler behavior • Experience with hardware security, side-channel analysis, or trusted execution environments • Knowledge of Intel Architecture and virtualization technologies (VMX/TDX) • Strong understanding of cryptographic principles and secure system design • Track record of published research, CVEs, conference presentations, or other industry-recognized security contributions Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Haifa Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *

Job Details: Job Description: Join us to help build the next generation of AI hardware solutions. You will be part of a highly skilled, agile team developing cutting-edge hardware for the AI domain, where we push the boundaries of what silicon can do for emerging AI workloads. With a startup-like culture, we move quickly and give engineers the opportunity to drive significant technical and business impact. We are intentional, fast adopters of AI as a working tool. We bring modern AI assistants and automation into every part of the verification flow — planning, stimulus and checker development, coverage analysis, debug and more — and we look to our senior verification engineers to help steer that evolution. If you are energized by defining things that have never existed before, value rigorous thinking, and want real scope and short feedback loops - you'll feel right at home here. This is a senior, hands-on role with broad technical influence. You will own verification for meaningful parts of the chip — complex IPs and subsystems — building the environments that take them to sign-off, with room to influence the methodologies and working flows we adopt as a team. Responsibilities: • Own verification strategy and execution for complex AI acceleration IPs and subsystems, grounded in deep understanding of the algorithms and microarchitecture under test. • Build verification environments, define verification plans, and drive coverage closure to sign-off. • Provide technical leadership and mentorship, and help shape the team's verification methodology and working flows, reviewing plans, environments, and results along the way. • Champion and advance the team's use of AI tools across the verification flow, finding where they add real leverage and helping the team adopt them well • Collaborate closely with architects, designers, DFT, and emulation/bring-up teams to ensure correctness from block to system level. Qualifications: • B.Sc. in Electrical Engineering, Computer Engineering, or equivalent. • 6+ years of hands-on functional verification experience, with a strong record of taking complex IPs/subsystems to sign-off. • Deep expertise in SystemVerilog/UVM, constrained-random and coverage-driven verification, and verification methodology and planning. • Strong intuition for working with AI tools and real interest in using them to advance the verification flow. • Demonstrated technical leadership: owning verification strategy, mentoring engineers, and driving decisions across teams. Advantage • Verification experience with accelerators, datapath, or compute-heavy IPs for AI/ML • Strong familiarity with the broader development cycle, including design, DFT, and bring-up. Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Haifa Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *

Job Details: Job Description: Join us to help build the next generation of AI hardware solutions. You will be part of a highly skilled, agile team developing cutting-edge hardware for the AI domain, where we push the boundaries of what silicon can do for emerging AI workloads. We are building this team from scratch within Intel. With a startup-like culture, we move quickly and give engineers the opportunity to drive significant technical and business impact. We are intentional, fast adopters of AI as a working tool, and actively use AI throughout our architecture, design, verification, and development workflows. If you are energized by defining things that have never existed before, value rigorous thinking, and want real scope and short feedback loops, you'll feel right at home here. This is a senior, hands-on role with broad technical influence. You will own central DFT aspects in our new family of chips and will define their architecture, planning and implementation. You'll also play a central role at defining and improving the methodologies and workflows we adopt as a team. Responsibilities • Define DFT architecture and strategy for complex AI acceleration IPs and subsystems, balancing test coverage, area, timing, and power. • Build the DFT implementation - scan, compression, boundary scan (JTAG), MBIST, and test access/control - and drive fault coverage closure to sign-off. • Lead ATPG & pattern generation • Contribute to the development of DFT methodologies and working flows, helping drive best practices across the team. • Champion and advance the team's use of AI tools across the DFT flow, finding where they add real leverage and helping the team adopt them well • Collaborate closely with design, verification, physical design, and product/test engineering teams, and support silicon bring-up, debug, and yield/quality analysis. Qualifications: • B.Sc. in Electrical Engineering, Computer Engineering, or equivalent. • 6+ years of hands-on DFT experience, with a strong record of driving DFT solutions from architecture through silicon bring-up. • Deep command of core DFT techniques: scan insertion, compression, ATPG, boundary scan (JTAG), and MBIST. • Strong intuition for working with AI tools and real interest in using them to advance the DFT flow. • Demonstrated ownership of complex DFT solutions and the ability to drive technical decisions across cross-functional teams. Advantage • DFT experience on large, high-performance, or AI/ML accelerator designs. • Hierarchical DFT, low-power test, in-system test, or silicon debug/bring-up experience. • Strong familiarity with the broader development cycle, including design, verification, and physical design Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Haifa Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *

Job Details: Job Description: The Role and Impact In this role as a Manufacturing Technician, you will play a pivotal part in Intel's production process by executing critical manufacturing and assembly tasks to ensure products meet industry standards and customer specifications. You will operate production equipment, optimize processes, and conduct quality checks to maintain efficiency and uphold product integrity. Your contributions will directly support Intel's innovative manufacturing operations, driving consistent quality and operational excellence. Business group This position is part of Intel Foundry, a business group dedicated to delivering world-class manufacturing capabilities that power Intel's technologies and products. Intel Foundry supports the company's broader goals through precision-driven production and cutting-edge manufacturing solutions. Join a high-performing team committed to enabling Intel's innovation and leadership in the semiconductor industry. Key Responsibilities - Perform assigned product manufacturing and assembly tasks in compliance with standard operating procedures and industry practices. - Operate production equipment, both remotely and internally, ensuring optimal functionality and efficiency. - Execute quality control evaluations on raw materials and finished products to confirm adherence to established standards. - Collect, analyze, and leverage operating data to conduct equipment adjustments and optimize production processes. - Conduct regular inspections and maintenance activities to ensure equipment availability and reliability. - Set up and calibrate production equipment to maximize output and quality. - Support the installation, qualification, and training of new or reused production equipment. - Collaborate with the Manufacturing Operations Manager and peers to meet production output requirements and escalate issues as needed. - Implement process improvements, troubleshoot production line events, and monitor technological health and stability. - Maintain accurate production logs and required documentation. Qualifications: Minimum Qualifications • Practical Engineer in a relevant field with hands-on experience or demonstrated knowledge in manufacturing, production, or technical environments. (Experience may be gained through industry roles, internships, academic projects, coursework, or hands-on training. • Proficiency in operating and troubleshooting manufacturing equipment. • Familiarity with quality control methods and standards. • Experience using automated systems to monitor and adjust processes. • Basic understanding of production documentation and record-keeping standards. Preferred Qualifications • Strong communication and collaboration skills demonstrated through team-based projects or work experience. • Proven ability to identify process improvements and implement solutions effectively. • Experience working in a fast-paced manufacturing environment with a focus on deadlines and quality standards. • Desire to contribute to a culture of continuous learning and innovation. If you're ready to take your manufacturing expertise to the next level, make a meaningful impact, and grow your career in a dynamic and inclusive environment, we encourage you to apply today. Job Type: Tech Grad Shift: Shift 9 D (Israel) Primary Location: Israel, Kiryat-Gat Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. *

Job Details: Job Description: Intel is a leading technology company specializing in cutting-edge wireless communication solutions. We are seeking a highly motivated Wireless Connectivity System Engineer to join our engineering team. In this role you will primarily own system-level integration, validation, and optimization of wireless connectivity SoCs and platforms, including Wi-Fi, Bluetooth, and related technologies, while also contributing to the system architecture and definition of next-generation products. You will work at the intersection of hardware, firmware, software, and architecture, driving issues from early bring-up through production readiness, and feeding real-world integration and debug insights back into system specifications, architectural trade-offs, and future product definition. Key Responsibilities: System and Architect • Lead and contribute to end-to-end system integration of wireless connectivity SoCs and platforms. • Drive silicon bring-up, feature enablement, and system readiness across development milestones. • Contribute to the definition of the system architecture of wireless SoC products, considering power efficiency, performance, and scalability. • Integrate wireless IPs across HW, FW, driver, and OS layers to ensure correct system behavior. • Translate integration and validation learnings into architectural improvements and next-generation product definition. Debug, Validation & Root Cause Analysis • Perform system-level debugging of complex issues spanning analog, digital, firmware, and software domains. • Develop and execute validation strategies, test plans, and stress scenarios to ensure product quality and robustness. • Conduct deep root cause analysis and drive fixes across cross-functional teams. • Leverage AI/ML-based tools and data analytics to accelerate log analysis, anomaly detection, and automated failure triage. Performance, Power & Reliability Optimization • Analyze and optimize performance, latency, throughput, power consumption, and coexistence behavior at the system level. • Identify and address performance bottlenecks, ensuring the SoC meets stringent performance requirements. • Support trade-off decisions between features, power, performance, and schedule. Cross-Functional Collaboration • Work closely with architecture, design, firmware, software, validation, and product teams to align system requirements and resolve integration challenges. • Act as a technical focal point for system-level wireless connectivity topics. Documentation & Technical Leadership • Produce clear technical documentation, integration guidelines, design guidelines, and issue reports. • Present findings and recommendations to engineering and management stakeholders. • Contribute to process improvements and best practices for system integration, validation, and architecture. • Drive adoption of AI-assisted engineering practices and automation to improve debug, validation, and documentation efficiency. Qualifications: Minimum Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Experience in system integration or system validation of complex SoC-based products. Exposure to system architecture, system definition, or specification work for SoC or wireless products. Strong understanding of wireless connectivity technologies (Wi-Fi, Bluetooth, coexistence – advantage). Hands-on experience with debug tools, lab equipment, and system-level validation environments. Familiarity with semiconductor technologies and SoC development processes. Strong analytical, problem-solving, and debugging skills. Excellent communication skills and ability to work effectively in a cross-functional environment. Working proficiency with Python / scripting and AI-GenAI tools to automate data analysis, debug, and validation flows. Experience applying AI / machine learning techniques to log analysis, anomaly detection, or automated failure triage. Hands-on use of GenAI / LLM-based assistants for code, test, and documentation generation. Familiarity with AI/ML acceleration and on-device inference considerations in SoC architecture. Preferred Qualifications (Advantage) Experience with wireless SoC bring-up or post-silicon validation. Experience defining system architecture or system specifications for wireless products. In-depth knowledge of wireless communication protocols and standards. Familiarity with firmware, drivers, or low-level software. Understanding of power management, performance analysis, and system trade-offs. Experience with system-level modelling and simulation. Experience working across multiple product generations or platforms. If you are passionate about wireless technology, enjoy solving complex system-level problems hands-on, and want to influence the architecture of future wireless SoCs, we encourage you to apply for this position at Intel. Join us in shaping the future of wireless communication solutions. Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Petah-Tikva Additional Locations: Israel, Haifa Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *

Job Details: Job Description: Our team is dedicated to optimizing Intel’s cutting-edge process technology to meet the rapidly evolving needs of next-generation silicon designs. Operating at the intersection of process and design development, we drive continuous innovation in both physical design and methodology. We partner closely with Core and SoC design teams worldwide to drive both process and product-level optimization - directly enabling Intel to deliver highly competitive, high-performance and low-power products. Role Overview As a Physical Design & PPA Optimization Engineer, you will play a key role in achieving best-in-class Power, Performance, and Area (PPA) for Intel IPs. You will be responsible for identifying optimization opportunities, developing physical design optimization methodologies, executing the full physical design flow to evaluate PPA landing zones on new Intel process technologies, and translating findings into actionable recommendations that influence strategic decision-making and product direction. Key Responsibilities • Define and implement DTCO experiments to evaluate the interaction between process technology and physical design implementation. • Define and develop design optimization methodologies across all physical design flow domains, such as placement, CTS, routing, and timing closure • Run the full PnR flow to evaluate new technology impacts on PPA metrics. • Identify trade-offs and optimization opportunities at the device, cell, and block Qualifications: Minimum Qualifications • BSc or MSc in Electrical Engineering, Computer Engineering, or a related field • Hands-on experience in physical or circuit design • Basic scripting experience using Python, Tcl, or a similar language • Strong analytical and problem-solving skills • Ability to analyze implementation results and communicate conclusions clearly Preferred Qualifications • 2+ years of experience in physical design or circuit design • Familiarity with physical design implementation flows and methodologies • Solid understanding of transistor, cell, and block-level PPA trade-offs • Experience developing physical design methodologies and analysis tools #LI-DL1 Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Haifa Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. *