Altera

Job Details: Job Description: • Conducts or participates in multidisciplinary research in the design, development, testing and utilization of information processing hardware and/or electrical components, mechanisms, materials, and/or circuitry, processes, packaging, and cabinetry for central processing units (CPUs) and/or peripheral equipment. • Prepares specifications, evaluates vendors, and analyzes test reports. • Ensures products conform to standards and specifications. • Develops plans and cost estimates and assesses projects to analyze risk. • Develops procedures, analysis and design for computer components, products, and systems. • Initiates, guides, and coordinates overall design and development of new ideas and products. • Responds to customer/client requests or events as they occur. Develops solutions to problems utilizing formal education and judgement. Qualifications: • Master’s degree or bachelor’s degree in engineering. • Hands-on laboratory support experience. • Student position. Job Type: Student / Intern (Fixed Term) Shift: Shift 1 (Israel) Primary Location: Jerusalem, Israel Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Job Details: Job Description: Altera is seeking a skilled DFT Design Engineer to contribute to the design and implementation of Design-for-Test (DFT) solutions for complex integrated circuits, ensuring high test coverage and efficient manufacturing test. • Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN). • Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including SCAN, MBIST). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. • Optimizes logic to qualify the design to meet test-coverage, DPM, and test-time/vector-memory reduction goals as well as design integrity for physical implementation. • Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. • Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high-quality integration of the IP block. • Collaborates with post-silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation. Experiment in DFT for mix signal IP required. Qualifications: • Minimum Bachelor's degree in Electronics Engineering. • At least 4 years of experience in DFT. • Strong experience in Scan Architecture, Scan Insertion, and ATPG execution. • Experience defining and implementing scan procedures. • Good experience with Mixed-Signal IP DFT. • Hands-on experience with MBIST implementation and MBIST validation. • Experience in RTL design, DFT integration, verification, and supporting DFT activities at IP/SoC level. Job Type: Regular Shift: Shift 1 (Israel) Primary Location: Jerusalem, Israel Additional Locations: TLV Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Job Details: Job Description: We're looking for talented, self-motivated engineers to join our Design Verification (DV) team in a junior or mid-level position. We work on some of the most technically challenging silicon in the industry, spanning digital and analog design, DSP pipelines, and firmware-hardware co-verification. What We Build Our team develops and verifies high-speed SerDes IP, the physical layer technology that moves data at speeds from 10Gbps to 100Gbps+ across PCIe, Ethernet, and other industry-standard interfaces. Getting this right matters, the world's data moves through what we build. What You'll Work On • Constrained-random and coverage-driven verification of complex high-speed SerDes mixed-signal IP, including advanced verification environment development • Validation of DSP datapaths • FW/HW joint verification • Leveraging AI-assisted tools as a core part of your daily engineering workflow What We're Looking For • Bachelor's degree in EE, CE, or CS — recent graduate with a strong academic record • Solid grasp of digital design, computer architecture, and software programming • Analytical mindset — you enjoy root-causing problems, not just finding them • Ability to thrive in a dynamic, multi-disciplinary environment • Hands-on exposure to SystemVerilog/UVM or Python — a significant advantage, but not required What We Offer • A collaborative and innovative environment where great ideas come from every level of the team • A great place to work — we take the work seriously, and each other's success personally • Exposure to the full verification lifecycle — from spec to tape-out sign-off • A team culture that embraces modern tooling, including AI-assisted engineering, as a competitive advantage • A real growth path from day one Qualifications: • Bachelor's degree in electrical engineering, Computer Engineering, or Computer Science • 0–3 years of industry or academic experience in hardware design or verificationNice to Have • Hands-on experience with SystemVerilog/UVM • Python scripting for verification automation • Familiarity with mixed-signal or analog simulation concepts • Knowledge of high-speed protocols such as PCIe or Ethernet • Prior internship or experience in RTL design or verification • Strong academic record; top graduating students are encouraged to apply Job Type: Regular Shift: Shift 1 (Israel) Primary Location: Jerusalem, Israel Additional Locations: Haifa, Israel, TLV Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Job Details: Job Description: We are seeking a skilled and detail-oriented Analog Layout Designer to join our engineering team. In this role, you will be responsible for designing complex layouts of analog signal circuits based on rigorous design specifications. You will execute comprehensive verification flows to ensure top-tier performance, reliability, and manufacturability, while collaborating closely with cross-functional teams to optimize area, power, and yield. Key Responsibilities • Layout & Floorplanning: • Design complex layouts of analog signal circuits meeting strict design specifications. • Design and analyze floorplans, power grids, ESD protection structures, and bumps for analog blocks. • Perform micro-floorplanning and detailed signal planning for complex analog circuits, ensuring proper shielding and device matching for critical signals. • Verification & Reliability: • Run complete sets of design verification tools to check process design rules (DRC/LVS). • Perform critical reliability checks, including electromigration, voltage drop (IR drop), ESD, and other advanced layout-dependent effects. • Methodology & Innovation: • Develop and drive new, innovative analog layout methodologies to continuously improve layout productivity, efficiency, and quality. • Troubleshoot a wide variety of challenges ranging from design anomalies to tool, flow, and methodology issues. • Cross-Functional Collaboration: • Partner with analog circuit designers, process technology teams, and package design engineers to align on specifications and plan deliverables. • Negotiate layout trade-offs effectively to optimize for area, power, reliability, and overall performance. Qualifications: Experience: Proven experience in analog and mixed-signal integrated circuit (IC) layout design. Technical Expertise: • Strong proficiency in custom layout tools (e.g., Cadence Virtuoso or equivalent). • Deep understanding of physical verification tools (Calibre or equivalent) for DRC, LVS, ANT, and ERC. • Expertise in advanced reliability verifications (EM/IR, ESD, thermal effects). • Solid knowledge of advanced semiconductor process nodes and related layout techniques (matching, shielding, guard rings, common-centroid layout). Soft Skills: Excellent problem-solving abilities, strong communication skills, and the ability to thrive in a collaborative, cross-functional team environment. Job Type: Regular Shift: Shift 1 (Israel) Primary Location: Haifa, Israel Additional Locations: TLV Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Job Details: Job Description: Altera, a leader in programmable solutions from cloud to edge, delivers cutting-edge FPGA, CPLD, and IP technologies. We drive innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure. Our mission is to empower engineers to design and deploy advanced systems with unmatched flexibility and performance. We are seeking a Signal and Power Engineer to join our SERDES Analog team in Haifa and support the integration of mixed-signal and high-speed SERDES IPs into full-chips silicon design, packages and PCBs. This role is ideal for early-career engineers looking to grow their hands-on design skills while working alongside experienced engineers. • SERDES IP System Simulation Support: SERDES IPs reference channel definition, creation and parameters extraction under guidance from a senior engineer • SERDES IPs Integration Support: Silicon IPs parameters review and validation with conjunction the package and PCBs design according to the interface specification • Package and PCB Design Verification: Participate in the package and PCB schematics and layouts review activities, review simulations results, and help debug and resolve failing simulations • Mixed-Signal and Channel Simulation: Learn and apply Signal and Power Integrity environments concepts, including SIPI circuits, channels and IOs simulation to support the optimisation of the package and PCB designs • Design Quality and Optimization: Support efforts to meet power, performance and signal integrity requirements, ensuring the package and PCB designs are suitable for implementation • Cross-Team Collaboration: Work with internal teams to ensure successful IPs, packages and PCBs integration and high-quality design delivery Qualifications: • B.Sc or M.Sc Electrical Engineer graduate from well recognized universities. • Strong background in electromagnetic and waves theory of physics • High motivated junior engineer with previous gathered experience from the university projects • Team players who enjoy big challenges • Ability to the study and implementation of the learned material and theory in the multidisciplinary domains: Analog and Digital Electronics, Signal and Power Integrity • Applicants must include their academic grades sheet as part of the application • Experience in ASIC package design, including optimizing pinouts, stack-ups, and high-speed routing • Knowledge of silicon floor planning, signal integrity (SI), and power integrity (PI) considerations • Hands-on experience with advanced testing and measurement equipment, including oscilloscopes and TDR/VNA analyzers • Understanding of high-speed signal design and power distribution networks (PDN) Job Type: Regular Shift: Shift 1 (Israel) Primary Location: Haifa, Israel Additional Locations: Jerusalem, Israel, TLV Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Job Details: Job Description: AMS PDE (Server/IP Design Team) is looking for a CAD/DA student to join our team, developing the industry's best high-speed communication devices! Take part in our design innovation chips, enjoy working in a meaningful, growing, and highly professional environment where you make a significant impact in a technology-focused company. our responsibilities will include, but not be limited to: • Supporting and stabilizing our tools across our global teams to enable our business transformation, design, development, and testing. • Using Cursor (any AI platform) & scripts to generating detailed analytics dashboards. • Collaborating with development teams and customers to enable and enhance EDA tools. • Troubleshoot and enhance version management systems, EDA tools, and issues with complex physical design flows. Qualifications: • Information system student with at least 2 years until graduation. • Good communication skills with different stakeholders. • Familiar with databases: MS SQL Server, Power BI. • Familiar with AI platforms: Cursor, Copilot & more • Solid programming and scripting languages such as Python, Tcl, C/C++. • Experience working on Linux environments and EDA Tools. • Good English, self, fast learner & motivated for success. Job Type: Student / Intern (Fixed Term) Shift: Shift 1 (Israel) Primary Location: TLV Additional Locations: Jerusalem, Israel Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Job Details: Job Description: Join Altera Israel as an Experienced Firmware Development Engineer Altera Israel is growing and looking for a talented Firmware Development Engineer to be a part of our team. If you're passionate about embedded development, signal processing, and high‑speed communication, this role is for you. About the Role You will develop firmware for a multi‑protocol high‑speed SERDES (up to 256Gbps), working closely with system, analog, and logic design teams on PHY technologies such as Ethernet, PCIe, OIF, JESD, PON and more... Responsibilities • Own the development of firmware governing SERDES DSP and analog blocks, ensuring seamless interface management with higher‑level system layers. • Implement and integrate signal‑processing and communication algorithms. • Support PHY bring‑up, debugging, and system‑level validation. • Collaborate with analog, logic design, and system teams to ensure smooth HW‑FW integration. Qualifications: • B.Sc. in Electrical Engineering or Computer Engineering. • Strong background in signal processing and communication systems. • 4+ years of hands‑on embedded/firmware development (C/C++). Advantage: • Tensilica / RISC‑V experience. • Knowledge of Verilog. • Experience in multi‑protocol PHY development. Job Type: Regular Shift: Shift 1 (Israel) Primary Location: Jerusalem, Israel Additional Locations: TLV Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Job Details: Job Description: Undergraduate student learning Electrical Engineering in University from year 3. The student will join Israel analog design team focusing on chip level high-speed analog circuits such as ADC, AFE, PLL, DCO, high-speed amplifiers, high-frequency clocking circuits and more. The student should have a solid background and understanding in linear circuits, digital circuits as learned in relevant university courses. Qualifications: Job Type: Student / Intern (Fixed Term) Shift: Shift 1 (Israel) Primary Location: Haifa, Israel Additional Locations: Jerusalem, Israel Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Job Details: Job Description: Altera is seeking a highly motivated and skilled Logic Designer to contribute to the development of cutting-edge programmable logic devices. This role involves designing, verifying, and implementing complex digital logic for our next-generation FPGA products. Job Title: Senior Logic/DSP Design Engineer – Mixed Signal Location: Israel Department: Analog Mixed Signal Serdes (AMS) About the Role We are seeking a Senior Logic/DSP Design Engineer to develop digital logic and DSP algorithms supporting mixed-signal IP blocks (e.g., high-speed SerDes, ADC/DAC digital, calibration engines, and control logic). This role bridges the digital and analog domains — translating system-level and DSP algorithms into synthesizable RTL, and working closely with analog/mixed-signal architects to close the loop on calibration, equalization, and adaptive control. Key Responsibilities • Micro-Architect Design and implement digital logic (RTL) for mixed-signal subsystems — calibration state machines, digital filters, adaptive equalization, clock/data recovery digital loops, etc. • Collaborate with analog design teams to define digital-analog interfaces, calibration flows, and control logic. • Perform RTL-to-gate synthesis, timing closure, and low-power design techniques for mixed-signal digital blocks. • Build and maintain block level verification environments (Verilog) for digital logic tied to analog behavior (mixed-signal verification, AMS co-simulation). • Support silicon bring-up and debug — correlating digital logic behavior with analog measurements in the lab. • Document architecture, algorithms, and design decisions; participate in design and code reviews. • Mentor junior engineers on digital design practices within a mixed-signal flow. Qualifications: • BSC/MSC in Electrical Engineering. • 7+ years of experience in digital logic design, with exposure to mixed-signal or DSP projects. • Strong RTL design skills (Verilog) and synthesis flow experience • Solid understanding of DSP fundamentals (filtering, sampling, quantization, timing recovery). • Familiarity with mixed-signal verification methodologies (AMS simulation, Verilog-AMS, real number modeling). Preferred Qualifications • Experience with high-speed SerDes, PCIe, DisplayPort, Ethernet or similar interface standards. • Exposure to calibration/adaptation algorithms for ADCs, DACs, or equalizers. • Familiarity with low-power design techniques and static timing analysis (STA). • Experience working directly with analog designers on digital-analog co-design. Job Type: Regular Shift: Shift 1 (Israel) Primary Location: Haifa, Israel Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Job Details: Job Description: As the AMS SerDes Layout team manager you are expected to, • Lead and develop a team of layout engineers and first-line managers, fostering a high-performance, collaborative culture • Own layout execution for AMS design • Partner with circuit designers, physical design engineers, and program managers to align on schedules, priorities, and quality targets • Drive continuous productivity and quality improvements • Manage headcount planning, performance reviews, and career development for direct and indirect reports • Represent the layout team in cross-functional technical and program review • Communicate status, risks, and mitigation plans clearly to senior leadership Qualifications: • 10+ years of experience in layout, circuit design, physical design, or related disciplines • Proven experience managing both individual contributors and team leads / managers • Experience in managing program execution • Excellent communication and stakeholder management skills - able to influence across engineering, program management, and leadership Job Type: Regular Shift: Shift 1 (Israel) Primary Location: Jerusalem, Israel Additional Locations: Haifa, Israel Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Job Details: Job Description: Job Description: Altera, a leader in programmable solutions from cloud to edge, delivers cutting-edge FPGA, CPLD, and IP technologies. We drive innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure. Our mission is to empower engineers to design and deploy advanced systems with unmatched flexibility and performance. We are seeking a Student/Junior Signal and Power Engineer to join our SERDES Analog team in Haifa and support the integration of mixed-signal and high-speed SERDES IPs into full-chips silicon design, packages and PCBs. This role is ideal for early-career engineers looking to grow their hands-on design skills while working alongside experienced engineers. Responsibilities • SERDES IP System Simulation Support: SERDES IPs reference channel definition, creation and parameters extraction under guidance from a senior engineer • SERDES IPs Integration Support: Silicon IPs parameters review and validation with conjunction the package and PCBs design according to the interface specification • Package and PCB Design Verification: Participate in the package and PCB schematics and layouts review activities, review simulations results, and help debug and resolve failing simulations • Mixed-Signal and Channel Simulation: Learn and apply Signal and Power Integrity environments concepts, including SIPI circuits, channels and IOs simulation to support the optimisation of the package and PCB designs • Design Quality and Optimization: Support efforts to meet power, performance and signal integrity requirements, ensuring the package and PCB designs are suitable for implementation • Cross-Team Collaboration: Work with internal teams to ensure successful IPs, packages and PCBs integration and high-quality design delivery Qualifications: Minimum Qualifications • B.Sc or M.Sc Electrical Engineer at well recognised universities with average grades above 85with one years till graduation • Strong background in electromagnetic and waves theory of physics • High motivated junior engineer with previous gathered experience from the university projects • Team players who enjoy big challenges • Ability to the study and implementation of the learned material and theory in the multidisciplinary domains: Analog and Digital Electronics, Signal and Power Integrity • Applicants must include their academic grades sheet as part of the application Preferred Qualifications for the Student • Basic or deep knowledge in Keysight ADS and HSPICE simulation setup creation and running • Basic or deep hands-on experience in the Ansys HFSS, Cadence Clarity or similar Electromagnetic Simulation tools – setups creation and parameters definition, simulation running • Basic or deep knowledge of the PCIe and IEEE Ethernet specification ---This is a student position which is relevant for Israel Only--- Job Type: Student / Intern (Fixed Term) Shift: Shift 1 (Israel) Primary Location: Haifa, Israel Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Job Details: Job Description: We are seeking an experienced IT End User Support to provide advanced technical support and leadership within our IT operations team. This role is responsible for resolving complex technical issues, mentoring and developing team members, and ensuring the stability, security, and performance of end-user systems and infrastructure. Key Responsibilities • Provide Tier 2/3 support for hardware, software, and network issues • Troubleshoot and fix escalated issues quickly to keep things running smoothly • Set up and maintain laptops, mobile devices, and peripherals • Support systems like Active Directory, email, and VPN access • Handle printer troubleshooting and fixes • Help users with conference room AV setups (Crestron, Logitech, etc.) • Jump in on IT projects like upgrades, migrations, and deployments • Troubleshoot login issues, Wi-Fi problems, and application errors • Document solutions and processes for the knowledge base/SOP • Work with other teams to improve overall IT support and user experience Qualifications: Required Qualifications • Bachelor’s Degree in Information Technology, Computer Science, or related field (or equivalent experience) • 3+ years of experience in IT support or help desk roles • Strong knowledge of Windows and/or macOS environments • Experience with Active Directory, Office 365, and endpoint management tools • Solid understanding of networking fundamentals (TCP/IP, DNS, DHCP, VPN) • Proven ability to troubleshoot complex technical issues • Excellent communication and customer service skills Preferred Qualifications • Industry certifications (e.g., CompTIA A+, or Microsoft certifications) • Experience with ticketing systems (Service-Now) • Familiarity with cloud platforms such as Azure, Microsoft Intune • Experience supporting remote or hybrid work environments Key Competencies • Problem-solving and analytical thinking • Strong attention to detail • Ability to prioritize and manage multiple tasks • Customer-focused mindset Work Environment • On-site • May require occasional after-hours support or on-call rotation Job Type: Regular Shift: Shift 1 (Israel) Primary Location: Jerusalem, Israel Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Job Details: Job Description: • Performs functional and system validation in lab for mixed signal IP, to ensure design will meet specification requirements and deliver best product to costumer. • Develops IP validation environment to ensure coverage to confirm to mixed signal microarchitecture specifications. • Executes validation plans, defines runs, develop recipe and replicates issues and root causes with FW, system and analog deign team. Qualifications: • Bachelor's Degree. • Electromic engineer student. • Deep knowledge in digital circuit and timing. • Fast learning capabilities, creative and team player. Job Type: Student / Intern (Fixed Term) Shift: Shift 1 (Israel) Primary Location: Jerusalem, Israel Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.